Aptina Proposes In-Pixel Ramp for ADC

Aptina's patent application US20150009379 "Imagers with improved analog-to-digital circuitry" by Hai Yan and Kwang-bo Cho adds a capacitor on FD of the pixel to deliver ramp for the ADC:

"Conventional ramp circuitry applies the ramp voltage to a capacitor at the input of the comparator of the sample-and-hold circuitry. However, such an arrangement requires a high pixel supply voltage in order to support a wide range of pixel output signals sampled onto the capacitor (e.g., sufficient to support the well capacity of the pixel). The capacitor is required to have a capacitance sufficient to satisfy noise requirements such as a maximum amount of thermal (k*T/C) noise, which in turn requires the ramp circuitry to have high driving capability for driving the large capacitor. Conventional capacitors used in ramp circuitry can be hundreds of femtofarads (fF). The large sample-and-hold capacitor also occupies valuable circuit area of the imager. In addition, the pixel array is typically read by scanning pixel rows in sequential order. This sequential scanning can lead to row-dependent noise in the image output signals of the pixel array. For example, transient noise in a power supply signal is consistent throughout the pixels of a row but varies between rows. It would therefore be desirable to provide imagers with improved pixel readout and analog-to-digital conversion capabilities."