Tuesday, January 20, 2015

Toshiba Proposes Superlattice Underneath Transfer Gate

Toshiba patent application US20150008482 "Semiconductor device and manufacturing method thereof" by Motoyuki Sato says that making SiGe superlattice under transfer gate can drastically reduce the influence of SiO2/Si interface traps that potentially can capture photoelectrons during the transfer. The dark current and white pixel defects are also said to be reduced:

Posted by Vladimir Koifman at 21:14

1 comment:

  1. AnonymousJanuary 21, 2015 at 3:58 AM

    1. may be you can avoid issues with interface states; however, you may run into issues with the stress at the Si/SiGe interface.
    2. since most of the band offset in this system is in the valence band, therefore electrons are not well confined in the layer you'd like. unless you design a hole based detector you can't exploit this idea in practice.

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