Wednesday, February 20, 2019

Albert Theuwissen Reviews ISSCC 2019 - Part 2

The second part of Albert Theuwissen's review of image sensor session at ISSCC 2019 talks about “A Data Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection” by Christopher Young, Alex Omid-Zohoor, Pedram Lajevardi, and Boris Murmann from Stanford University and Robert Bosch:


“A 76mW 500fps VGA CMOS Image Sensor with Time-Stretched Single-Slope ADCs Achieving 1.95 e– Random Noise” by Injun Park, Chanmin Park, Jimin Cheon, and Youngcheol Chae form Yonsei University and Kumoh National Institute of Technology, Korea:

14 comments:

  1. the time-stretched SS-ADC is a very interesting idea! Congrats to Prof. Chae and his team!

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  2. I wonder about the time stretcher amp. Did they give details about it ?

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    1. I guess that time stretcher is a clock multiplier circuit like a PLL/DLL

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    2. I've added a slide explaining the time stretcher concept.

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  3. Why not 5bit+5bit combination instread of 6bit+4bit in the second paper?
    Total clock cycles will be further reduced to 64 instead of 80.

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    1. I'd guess the limiting factor is the time stretcher inaccuracies, controls rise/fall time, and column-to-column variations. If not that, one could build a hierarchical chain of time stretchers and add another 5b to resolution.

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    2. Albert Theuwissen - Harvest ImagingFebruary 22, 2019 at 12:22 PM

      In the talk the authors mentioned that 6+4 is the optimum (in the case of a 10-bit). It is not only the number of clocks, but also the clocking frequency that counts.

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    3. The faster the clock, the harder it must be to control inaccuracies due to rise/fall time, comparator speed etc ... . You may get some missing codes.

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  4. That would be interesting to have INL & DNL FOM. Did the authors communicate on that ?

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    1. Not that I know of. They also did not address the issues of metastability or ambiguity. For example, what happens if MSB comparator changes at exactly clock edge - the MSB counter might count this as "1" while LSB logic might see it as "0" in that clock cycle.

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  5. Both INL and DNL are shown. The issue of metastability is solved by measuring the time difference between the comparator output and NEXT clock edge of the counter.

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    1. So, what happens when the time form the comparator switching is very close to the clock edge, almost simultaneously? How do you decide what is THIS clock edge and what is the NEXT one?

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  6. Both INL and DNL are shown.

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  7. Care to share INL & DNL figures ?

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