Article on Pixel Scaling: DTI, High-k, 0.6um Pitch, More

Semiconductor Engineering site publishes an article "Scaling CMOS Image Sensors" by Mark Lapedus. Few quotes:

Recently, vendors have ironed out the issues and the pixel scaling race has resumed. In 2018, Samsung broke the 1µm barrier with 0.9µm, followed by Sony with 0.8µm in 2019, and Samsung with 0.7µm in 2020.

For sub-µm pixel scaling, the industry requires more innovations. “As pixels shrink, thicker active (silicon) is required to maintain a suitable photodiode size,” [TechInsights analyst Ray] Fontaine said in a recent presentation. “A key technology enabler for thicker active (silicon) is DTI and associated high-k defect passivation films.”

Making an image sensor with high-k films follows a traditional flow. What’s different is that high-k films are deposited over the liner in the DTI trenches.

For high-k and other processes, vendors take two different approaches in the fab—front-DTI (F-DTI) and back-DTI (B-DTI). “F-DTI uses a poly silicon gap fill, and the poly can have voltage bias for improved surface pinning. F-DTI can also have more thermal treatment for etch damage leakage reduction,” OmniVision’s [SVP of Process Engineering Lindsay] Grant said. “B-DTI uses high-k films with a negative charge to accumulate charge and pin the Fermi level at the surface, which then suppresses dark-current leakage. The high-k film process is atomic layer deposition (ALD). B-DTI typically uses an oxide gap fill, but some metal fill and even air gap have also been tried and used in mass production.”

Will pixel scaling continue? “It’s likely that pixel scaling will continue beyond 0.7µm,” Grant said. “As pixels shrink beyond 0.7µm, many aspects need to be optimized. Key items, such as B-DTI, high-energy implant for deep diode, optical structure shrink for color and microlens, will remain the focus for development. The more basic design rules that define in-pixel transistors and interconnects need to be updated.”

Another issue is that the pixel pitch for mobile sensors is approaching the wavelength of light. “Some people may consider this a limit for minimum pixel size,” Grant said. “For example, the 0.6µm pixel pitch is used in R&D today. This is smaller than the wavelength of red light at 0.65µm (650nm). So the question may arise, ‘Why shrink to sub-wavelength? Will there be any useful benefit for the camera user? Shrinking the pixel size to sub-wavelength does not mean there is no valuable spatial resolution information at the pixel level.’”

Grant pointed out that the optical structures for a 1.0µm pixel use many sub-wavelength features. “For example, narrow metal grids for crosstalk suppression and narrow dielectric walls for quantum-efficiency are seeing improvement through light guiding. This nano-scale optical engineering is already in current pixels and has been for many years, so moving to sub-wavelength is not such a revolution,” he said. “The limitation for continued shrink may come from the user benefit rather than the technology. Today, applications continue to find end user value in shrinking the pixel size, so this is driving the trend. As long as that continues, CMOS image sensor technology development will support that direction.”

The next big thing is pixel-to-pixel interconnects. Xperi is developing a technology called “3D Hybrid BSI” for pixel-level integration. Sony and OmniVision have demonstrated the technology.

“It enables more interconnects,” said Abul Nuruzzaman, senior director of product marketing at Xperi. “It allows pixel-level interconnect between each pixel of the sensor and an associated A/D converter. This allows parallel A/D conversion for all pixels. The connection provides high-density electrical interconnection between the stacked pixel and logic layers, allowing implementation of as many A/D converters as the number of effective megapixels. Hybrid bonding can also be used to stack memory with dedicated memory to each pixel.”