"This monograph introduces the reader into basic and advanced aspects of single-slope analog-to-digital converters (SS-ADC) applied in solid-state image sensors. It is based upon the developments that took place over the last three decades in this field. Already in the very early days of CMOS image sensors (CIS), the very first SS-ADC was implemented. The architecture of the SS-ADC is an appealing concept for column-level ADCs in a CIS. Especially the small silicon area occupied by the ADC and the low power consumption are very attractive features. Unfortunately the SS-ADC, as it originally was developed, is relatively slow. This monograph describes all advantages and limitations of the SS-ADC, as well as the various improvements mainly focusing on increasing the conversion speed. On academic as well as on industrial level various optimizations were proposed to make the devices not only faster, but also to increase their performance in terms of noise. Implementation of a digital correlated sampling technique or the application of multiple correlated sampling (without any hardware change) are a couple of examples how SS-ADCs contribute to improved image quality of the CIS.
Before diving into various architectures of a SS-ADC, the monograph starts with an overview of some basic building blocks of a CIS. Conceptual improvements are described, finally coming to the so-called “counting SS-ADC”. A relatively large section is devoted to the theoretical analysis of the latter architecture, because this device has a unique combination of speed and low noise, two critical performance parameters for a CMOS image sensor."
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