e2v proposes to split the PHD into two with the "accelerating gate" GA in between, as on Fig. 2. By applying multiple voltage pulses on GA the electrons can be moved in and out of it, as shown on Fig. 3.
"The electron multiplication takes place during the charge integration and in the photodiode itself in the sense that the electrons (photogenerated or resulting already from the impacts of carriers with atoms) are accelerated in turn from the photodiode towards the accelerating gate and from the accelerating gate towards the photodiode. During these movements, impacts with atoms of the semiconductor layer of the photodiode region or of the region located beneath the accelerating gate make other electrons in the valence band pass into the conduction band. These electrons lose energy during these impacts but they are again accelerated by the electric field that is present.
The number of alternations in potential applied to the accelerating gate defines the overall multiplication coefficient obtained at the end of an integration period T, i.e. between two successive pulses for transferring charge from the photodiode to the charge storage region."
Fig. 4 shows one of the possible pixel layouts with GA located in the middle of PHD.
Update: As said in comments, in 2009 Sanyo published a different idea of electron multiplying CMOS pixel. The idea is shown on the figure below:
Update #2: As EF said in comments, Sanyo presented its electron multiplying sensor at ISSCC 2009 (paper, presentation). The pixel structure and the gain non-uniformity are taken from the presentation slides:
Different architecture to do in-pixel multiplication was published by Sanyo in 2009. Though in Japanese, here is the paper. http://www.kec.jp/committee/johoshi/pdf/jyohoshi_211-1.pdf
ReplyDeleteNice reference & thanks!
ReplyDeleteQuestion: when the GA is on, the surface under the GA will not be pinned. How to cope with the surface dark current issue in this case???
ReplyDelete-yang ni
I guess GA can be mostly in off state. For example, if one applies 1000 GA pulses, each time keeping it on for 1us or less, the total "on" time is just 1ms.
ReplyDeleteAnother issue is that the GA is small, so the electrical field will be very localized arounr the edge. The EM factor should be small. Maybe for this reason that Sanyo prefered a complete TX.
ReplyDelete-yang ni
I think the Sanyo 2009 ISSCC paper (See digest pp 50-51) is easier to read since it is in English.
ReplyDeleteThe 60x gain image still looks surprisingly good.
By the way, I am fairly certain that a CMOS version of the Impactron device was openly discussed during a session of the IISW (CCD/AIS?) some time ago, following some presentation on an Impactron device or E2V device. Anyone else remember this?
ReplyDelete@ "The 60x gain image still looks surprisingly good."
ReplyDeleteThanks for the reference! The gain non-uniformity is almost independent of gain - see the graph in the Update #2 to the post. It's still quite high though.
I wonder if it can be used in Geiger mode. Then it could be an alternative to SPADs - with the exception of less precise photon arrival timing.
Impactron is TI EMCCD with virtual phase CCD cells. E2V is L3CCD using classic 3-4 phases CCD cells.
ReplyDeleteRight, and E2V device is, more or less, a virtual phase (JFET) implementation, while the Sanyo device is classic MOS implementation.
ReplyDeleteEric, TI EMCCD is based on virtual phase and E2V uses MOS structure. That is why E2V one has some aging effect.
ReplyDeleteI am sorry for not being clear.
ReplyDeleteThe E2V device shown above is basically a virtual phase device because it seems to use a pinned photodiode structure. Virtual phase by Jerry Hynecek predates pinned photodiode by Teranishi but they are more or less the same structure. Teranishi did not know of virtual phase at the time of inventing the pinned photodiode, and VP was for multiple transfers whereas PPD was for single transfer into a CCD register (now CMOS readout). Both VP and PPD are basically Junction Field Effect Devices. (I said JFET above but I added "T" by habit).
So, global shutter devices using 2 pinned photodiodes are really VP structures.
VP has its own problems as was well known back a long time ago, as do high gate voltage MOS devices used for EMCCDs. I wonder if the E2V EM-CMOS device has been successfully implemented? Seems there might be several operational problems, including good transfer since angled implants are more challenging for multiple directions.
I think that transfer efficiency on the corners is not the most critical problem. My concern is that if the GA is too small, only few of photoelectrons can participate to the EM process. If GA is large, it will impact a lot the FF.
ReplyDelete-yang ni
YN - I was not talking about CTE at the corners, just opposite edges. Your point about the well capacity of the avalanche gate GA is good. Another which your comment brings to mind is that the field at the corners may be much stronger than along any edge, so that the highest avalanche effect or even breakdown could occur there. Again, I wonder if there are any experimental results from this interesting device proposal.
ReplyDeleteThanks Eric ! Happy New Year to you and your family !
ReplyDeleteOne question on VP CCD: does the clocked phase invert the Si surface when it's in OFF state ? The holes can be supplied by the pinning layer on the virtual phase implants.
Thanks !
The VP CCD did use holes to invert the surface and suppress dark current. There was also some issue about those holes generating spurious charge during clocking due to impact ionization so that clocking was more complicated in practice than originally intended for scientific applications. The idea of using the holes to suppress dark current by quenching surface state traps was used later in the OPP, MPP, and AGP CCDs.
ReplyDeleteFor more information use Google Scholar and search for "virtual phase CCD spurious charge".
Thanks ! So the clocked phase in a VPCCD is basically a surface device, right ?
ReplyDelete-yang ni
No, not really. The signal charge resides in a buried channel. The holes at the surface are not signal charge.
ReplyDeleteThat is really my question: when the surface is inverted, the potential will pinned to zero. Do you mean that there is a partial N doping under the clocked phase electrode ? Otherwise there is no way to create buried channel.
ReplyDelete-yang ni