The design is realized for pixel pitch of 6.7µm. Power consumption per column [12 bit] ADC is 88 µW and sampling speeds larger than 50kS/s is supported.
The outline of the operation of the Two-Step Integrating ADC is explained below and an example conversion sequence is illustrated in Figure 3.1.
- In the first step, K-bit coarse conversion is performed using a ladder shaped ramp. When the decision is made, the ramp value is latched into a memory capacitor. Furthermore, the global counter value latched in the digital coarse memory block.
- Secondly the residue between the latched ramp value and the input voltage is compared to the fine ramp in the L-bit fine conversion phase. Likewise, when the decision is made global counter value is latched into the digital fine memory block.
- On the final step, coarse and fine conversion results are superimposed and fed to the output stage.
Milano Politecnico, Italy, publishes MSc thesis "Sigma-Delta Analogue-to-Digital converter for column-parallel CMOS image sensors" by Michele Sannino.
In this master’s thesis project a column-parallel ADC for high data-rate image sensors was designed using TowerJazz 0.18µm process.
The ADC was required to achieve 12 bits of resolution in the competitive conversion time of 1us. Other design specifications include a constraint on the maximum input noise, which had to be less than 100uVrms, and on the average power consumption, to be contained within 330uW. The converter, which was laid out in a column-parallel topology with 15um pitch, was also required to occupy an area smaller than 10,000um2 (hence its length should be smaller than 670um). Meeting this specification makes the ADC suitable to be implemented in a stacked chip in future developments, which would push further the limit of achievableframe-rate.
It's great that Politecnico Milano has released the thesis of Michele, a recent addition to our CIS design team at IMASENIC (http://www.imasenic.com), so everyone can read about his column-ADC work.
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