Thursday, February 12, 2009

Toshiba Staggered Pixel Presented at ISSCC

Tech-On! describes Toshiba 8MP 1.75um pixel sensor, which Toshiba presents at ISSCC these days. The sensor uses two innovations: staggered pixels and floating diffusion boost. Staggered pixel idea is supposed to improve Gr/Gb mismatch and is shown below:

I'm not sure what happens with RST signal routing in this scheme, it looks like the wiring should be duplicated. It might be not an issue, if SEL transistor is eliminated. The staggered pixel is claimed to improve Gr/Gb ratio from 94.9% to 99.7%.

Another innovation is the FD voltage boost, apparently achieved through the source follower gate capacitance. This is a nice idea, albeit a bit obvious.

Toshiba plans to commercialize a product that uses staggered pixel layout and FD boost in spring 2009 at earliest.


  1. staggered is mis-spelled

  2. Sorry, I've fixed this. T and R are too too close on the keyboard.

  3. Indeed, the select transistor is eliminated. It is an architecture with 5T for 2 pixels, or 2.5 T pixel.
    Here is some more data : 1P3M combined 0.11 um and 0.13 um proces, 1.75 um pixel, 1.4 V/lux.s, 7700 e- capacity and 2.6 e- rms noise.
    There was another Toshiba paper on a camera module with TSV interconnects. Main issues for TSV : cost, high-speed I/O, ESD and yield management.


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