MIT Prsesents 3D-Integrated Imager

EETimes: MIT presented 3D-stacked imager at ISSCC. The 1MP imager is based on 0.35up technology and has 8um pixel pitch with per-pixel through-silicon vias (TSVs),

The imager has two basic tiers, which consists of seven layers. The first two tiers are the 3-D imager. Tier 1 has 100% fill factor, deep-depletion photodiodes, thinned to 50um. Tier 2 consists of SOI-CMOS pixel readout and selection circuitry that is 3-D connected to Tier 1 photodiodes.

The remaining five layers have a multi-chip silicon stack, which includes two silicon chips with 64 12b pipelined analog-to-digital converters, a timing sequencer, tile address encoder, bias generators, I2C serial interface, and two 12b wide LVDS outputs running at 512-Mb/s.

The imager is connected to the stack via a gold stud bump array at a 500um pitch. The imagers can be tiled together to create larger arrays.