Tuesday, November 29, 2011

Altasens Adopts Berkeley DA FastSpice

Business Wire: Berkeley Design Automation announces that AltaSens has selected the company’s AFS Platform for full-circuit post-layout verification, block-level characterization, and device noise analysis of their high-definition (HD) and wide-dynamic-range CMOS image sensors.

"At AltaSens we have significant circuit verification challenges to deliver CMOS image sensors with the highest image quality along with lower noise and lower power in a cost-effective solution," said Manjunath Bhat, VP of Engineering at AltaSens. "With the AFS Platform we can run post-layout verification of our high-performance wide-dynamic-range HD CMOS image sensors with nanometer SPICE accuracy. When running AFS single core we get performance on par with our existing parallel simulator running on 8 cores."

The Analog FastSPICE is said to deliver SPICE accuracy 5x-10x faster than any other simulator on a single core and an additional 2x-4x performance with multithreading. For circuit characterization, the AFS Platform includes the device noise analysis and delivers near-linear performance scaling with the number of cores. For large circuits, it is said to deliver more than 10M-element capacity, the industry’s fastest near-SPICE-accurate simulation, and mixed- analog-digital co-simulation with leading Verilog simulators. Available licenses include AFS circuit simulation, AFS Transient Noise Analysis, AFS RF Analysis, AFS Co-Simulation, and AFS Nano SPICE.

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