Saturday, January 07, 2012

CMOSIS 2nd Patent on Ramp ADC Granted

CMOSIS announces that its second patent on ramp ADC has been granted. The US8040269 patent proposes to speedup column-level ADC converter by using just one ramp cycle to measure previously sampled column reset and signal levels:


Two counters count the clock cycles between the reference levels and the signal and reset levels, then the final value is calculated as the ratio between the two counters.

5 comments:

  1. Good idea anyway. It should be useful for large array where the RC of metal lines could be a problem for a fast ramp signal.

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  2. I didn't read the patent, but I'm pretty sure the equation at the bottom of the figure should read Final signal value = cntr_signal - cntr_reference.

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  3. Interesting! By dividing the result, it is made sort of clock independent.

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  4. The final cntr_signal includes implicit digital subtraction of V_reset from V_signal (e.g. digital CDS). Dividing by cntr_reference normalizes the measured cntr_signal to the full range between V_ref1 and V_ref2.

    I think the general idea is interesting, if fraught with peril. On the plus side, the A/D throughput is doubled. On the minus side, multiple design headaches come to mind immediately. Now where is my A/Dvil...?

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  5. Is CMOSIS applying this concept in their CMV line of sensors?

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