Thursday, January 19, 2012

ST Proposes Bias S&H to Reduce Noise

ST Micro patent Application US20120006973 proposes to sample bias voltages and currents and hold them between CDS reset sample and signal sample, so that any bias noise does is constant over CDS cycle and, thus, subtracted. For example, in case of pixel current bias it might look like this:


In case of some other generic bias voltage, S&H might look like this:

8 comments:

  1. this is called dynamic current miror proposed by E. Vittoz so many eayrs ago ...

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  2. The trick is not a dynamic mirror itself. It's in the timing when to sample the current and when to hold it.

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  3. I think that this patent is similar to Aptina's patent for a pixel bias circuit.

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  4. Would you mind to post Aptina's patent number?

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  5. Vladimir, I can use the dynamic mirror for the in-pixel source follower load. In this case, I'll get the same structure and effect.

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  6. Sure, dynamic mirrors are not new and were used before, with one timing or another. However, the ST application is much broader and talks about biases in general, including other reference voltages and currents. They all can cause the additional row noise.

    In fact, the ST's proposal has some disadvantages. Even if all biases are sampled, there is still substrate noise that can not be eliminated by sampling. After all, it affects the pixel output itself. In order to compensate this, one would better tie the sampled voltages to a combination of ground and substrate, depending on the particular bias voltage.

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  7. Did anyone find honeywell's patent on sampling voltage to reduce noise? I donot recollect the name of the patent. But it had similar mechanism to reduce noise.

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  8. This is so easy to think about.

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