Sony Proposes Column-Parallel ADC Crosstalk Reduction Approach

Sony patent application US20140022430 "Solid-state imaging device and manufacturing method" by Yosuke Ueno, Natsuko Seino, and Kenichi Takamiya discusses a crosstalk challenge between the adjacent column-parallel ramp ADCs. As pixel size shrinks, the column pitch becomes smaller, the neighboring comparator's transistors are closer and coupling capacitance becomes more of the issue. One possible solution is to add metal shields between columns. However, the shield takes a significant column area. So, Sony proposes to re-arrange the comparator transistors in the neighboring columns in such a way that part of the crosstalk is compensated:

Column Ramp ADC (background info, nothing new)

Column comparator input stage (background info, nothing new)

The capacitive coupling problem shown (background info, nothing new)

Coupling caps from the above shown in schematics (nothing new so far)

One of the improvement proposals, coupling is partially compensated

Schamatics of the compensated layout,
Note that each half-nmos gets couping to the opposite side
of the neighboring diff pair