Thursday, March 05, 2015

NHK and Forza Silicon Present 133MP/60 fps Sensor Internals

Business Wire: Forza Silicon announces that researchers at NHK presented the design architecture and specifications of the 133MP 60fps CMOS image sensor at ISSCC 2015. The image sensor presented by NHK was designed by Forza Silicon and fabricated using a 0.18 ┬Ám 3.3V/1.8V process with 1D stitching.

To date conventional image sensors for 8K applications have used 8 MP and 33 MP solutions in large optical formats. In order to eliminate the bulky lens/color-prism optical system of previous generation cameras, the team developed a single-chip 133 MP image sensor. The sensor takes advantage of Forza Silicon’s Gen 3 readout architecture to achieve frame frequency of 60 fps. The Gen 3 readout architecture uses a pseudo-column parallel design with 14b redundant successive approximation register ADCs to achieve a throughput of 128 Gb/s at full resolution and frame rate.

Our continued partnership with Forza Silicon through the years to support NHK has resulted in the success of a number of significant projects such as the development of the 133 MP sensor, and previously the 33 MP Super Hi-Vision image sensor. Forza’s dedicated support and its image sensor design expertise enabled us to achieve the Super Hi-Vision 8K single-chip camera — the largest pixel count of any video image sensor,” said Dr. Hiroshi Shimamoto, senior research engineer at NHK Science & Technology Research Laboratories (STRL).

The advanced research and development initiatives by NHK continue to push the boundaries for UHDTV broadcast experiences. NHK’s next-generation digital broadcast systems stem from their long heritage as the world’s premier R&D center for broadcast camera technology. The groundbreaking technologies we’ve jointly developed have evolved over a span of 10 years as a result of our tight collaboration, and Forza’s decades of design experience and wide selection of silicon-proven IP,” said Barmak Mansoorian, president & co-founder at Forza Silicon.


  1. how to explain in their measurement (see ISSCC slides), the SAR-ADC has a maximum 6LSB DNL?

  2. I think I recall the comment at ISSCC that at a little bit slower clock speeds the DNL comes under just some settling time issues that I imagine are easy to fix in a 2nd spin.

    Meanwhile, nice work in defining the state of the art Forza and NHK!

  3. I've seen the slides as well. Forza's engineers are VERY GOOD! My issue is that such conferences require NOVEL solutions, ideas, circuits presented by the speakers. This is clearly stated in the ISSCC submission rules. There is no such novelty in this work. Just a outstanding implementation of existing methods. This paper is good match for the IISW workshop. Said so, I'm very impressed by the results.

    Same thing the Sony's paper: perfect implementation, no novel circuits. The double ADC idea has been used in sCMOS sensors since long time.

    Dunno what is wrong with ISSCC lately..

  4. A muscular show indeed! The reviewers must be Arnold Schwarzenegger's fans.


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