News and discussions about image sensors
Great achievements, ziptronix, but please improve your powerpoint skills. These slides are terrible, especially the last one!
Does anyone know if this technology is used outside stacked image sensors? (I assume the answer is yes...) in which fields? Why is - for example - in memory-market effort going on to build stacked packages (e.g. Hybrid memory cube) with TCB-stacked dies and not 'the ziptronix way' (maybe the answer is that it is limited to 2 layers)? In terms of stacking, this seems to be a far more efficient way than single die thermo compression bonding...
My understanding is that the Ziptronix's patented technology is used in RF (see the IO Semi press release a few years, i think, back), some presumably high end tech with Raytheon, several years ago, and 3D memory with Tezzaron. I cannot see why it would be limited to 2 layers and it does seem a far better way to stack memory then chip on chip. Why aren't the memory guys using it? HMC is kind of like a Prius...good idea...horribly ugly execution.
Ziptronix DBI technology is not limited to 2 layers and you are correct that this is the perfect technology solution that the Memory guys need to strongly consider. The one that realizes this and adopts/executes will be the technology leader for years to come. DBI is a complete game changer.
Are these guys using this technology or something else?https://www-03.ibm.com/press/us/en/pressrelease/36125.wss
That is HMC and involves TSV's. This is a costly and yield challenging process. The beauty of the DBI process is it effectively eliminates TSV's (At least the HAR TSV's) and the process was developed centered around existing industry standard wafer fabrication processes and tools already in production today. Effectively extending the ROI of existing equipment in place.
You need TSVs if 3 or more silicon layers need to be interconnected. With DBI you stop at 2. TSVs are here to stay ;)
DBI has the ability to eliminate the need for all HAR TSV's. Your designer(s) simply need to design the layout with a DBI/3D solution in mind, then you are not limited to just 2 layers. Look at what Tezzaron is developing with the use of DBI Technology in DiRAM.
Do you have any white paper to support that claim? I think DBI can interconnect 2 silicon layers when the top metal of layer 1 faces the top metal of layer 2. Then, to reach layer 3 you need to make holes through layer 2, hence you need TSV...
Tezzaron does indeed use TSVs in DiRAM - but very tiny ones. The trick is that they don't go all the way though the wafer, just from the bottom level of wiring down through maybe 10 microns of silicon. Wafer thinning exposes the tips of the TSVs and then they stack another layer. Look here:http://www.memcon.com/pdfs/proceedings2014/TEC102.pdf
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