Albert Teuwissen continues to publish ISSCC 2011 reviews. The third part covers:
M.W. Seo ( Shizuoka University) "An 80mVrms Temporal Noise 82 dB Dynamic Range CMOS Image Sensor with a 13-to-19b Variable Resolution Column-Parallel Folding-Integration/Cyclic ADC"
C. Lotto (Heliotis) "A Sub-Electron Readout Noise CMOS Image Sensor with Pixel-Level Open-Loop Voltage Amplification"
Isn't it more efficient to use a sigma delta with inherent multiple sampling instead of folding or whatever other ADC architecture? And how can they obtain 19bit of resolution with a single ended(!) column level adc? Do they use special calibration techniques? Very curious to read the paper...
ReplyDeleteOne other thing is a seeming disconnect in numbers: 19 bit is more than 114dB of DR, while the sensor is said to have the DR of 82dB. Then, why does one need the extra 30+ dB from the ADC in this sensor?
ReplyDeleteI don't the proceeding of ISSCC, any one can provide a schematic of "A Sub-Electron Readout Noise CMOS Image Sensor with Pixel-Level Open-Loop Voltage Amplification" ??
ReplyDeletethanks a lot in advance