Invisage Reveals Few More Bits of its Technology

Invisage patent applications US20110228144 and US20110226934 have been published. The US20110228144 is titled "DARK CURRENT REDUCTION IN IMAGE SENSORS VIA DYNAMIC ELECTRICAL BIASING" and shows how Invisage plans to reduce sense node diffusion dark current in what looks like a typical 3T pixel:

Invisage approach is quite simple - precharge the sense node to zero voltage so that in the dark the sense node voltage is always zero. Here is the timing diagram and the description (I used slightly wrong pixel figure because it has better labeling. The photocurrent direction is wrong):

"During a first period labeled “True reset,” the diode, or charge store, is reset to a known reference point, by setting the reset electrode to high voltage (turning on the reset transistor M1). In embodiments, during the reset phase, the electrode vfilm (i.e., the biasing electrode) is set to a bias voltage that is higher than diode voltage, for example 3V (normal range from −5V to 5V). The pixel electrode diode is driven to be a lower voltage, for example 0V (normal range from 0V to 5V). This is achieved by setting VLEVEL to a low voltage.

During a second period labeled “Integration,” the electrode vfilm remains at the same voltage, for example 3V. Light induced photocurrent in the floating photodetector will drive the diode voltage higher. The photocurrent serves as a current source in this configuration. The use of a low voltage on the pixel electrode significantly suppresses the dark current of the pixel circuitry under a dark condition. VLEVEL is pulled back to high voltage such as 3V, to minimize leakage path of transistor M1, and to prepare for readout phase.

During a third period labeled “Read signal,” the electrode vfilm is brought to a higher level, such as 5V (normal range −5V to 5V). This will boost up the diode voltage to make sure the low voltage at diode node can be read out through the readout circuit, and thus maintain dynamic range for the readout path. Alternatively, a low VT readout transistor M2 (for example, threshold of 0V, with range of −1V to 1V) can be used to read out the low voltage, in which case the pulsing on common electrode is not necessary.

During a fourth period labeled “CDS reset,” the reset electrode goes high again, setting the diode voltage to the same known level. This is achieved by pulling VLEVEL to the same low voltage as in ‘true reset’ phase.

During a fifth period labeled “Read reset,” VLEVEL is pulled back high to allow M2 functions as a readout transistor. This phase is used to readout the reset level."

The idea is quite nice but what about Reset transistor M1 charge ingection variations due to pixel-to-pixel mismatch? One can not allow sense node to go negative, so the average sense node voltage should be high enough to keep worst case pixel in positive domain. This can easily be 50mV or so for the average pixel. At this voltage the dark current would be lower, but not zero.