Photo-Gates are Back, but in a New Form

MDPI paper "Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications" by Francois Roy, Andrej Suler, Thomas Dalleau, Romain Duru, Daniel Benoit, Jihane Arnaud, Yvon Cazaux, Catherine Chaton, Laurent Montes, Panagiota Morfouli, and Guo-Neng Lu from ST Micro, IMEP-LaHC, LETI-CEA, and University Lyon is a part of Special issue on the 2019 International Image Sensor Workshop (IISW2019). The paper proposes a solution of quite an important issue associated with deep high energy implants:

"Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance."