Sunday, August 02, 2009

sCMOS Group Emphasizes High DR, Again

PRWeb, Yahoo: sCMOS group released quite a technical PR explaining what is DR and how it's increased:

"The dynamic range of an image sensor is defined as the ratio of the maximum to minimum signal that can be measured. In practice, this is determined by the ratio of pixel full well capacity to the readout noise. Therefore, large pixel full well and small readout noise are both necessary for optimal dynamic range. In order to utilize the full well of a CMOS pixel, the amplifier gain must be kept low. For example, given a 1.5V swing on the output of the amplifier, a 30,000 electron signal will require a gain of 1.5V/30,000e- = 50uV/e-. This will allow measurement of the full well signal but will not allow for the lowest possible read noise. In order to get a very low readout noise and the resulting superior sensitivity, a value of 1500uV/e- would be ideal but this would mean that the largest signal would be limited to 1000e- maximum which is only 1/30th of the total well size. This leaves a quandary of whether to choose maximal sensitivity or high dynamic range imaging.

PCO, Andor and Fairchild together have taken a novel design approach in sCMOS technology by implementing both approaches simultaneously. sCMOS technology has a high-gain amplifier to get the lowest possible noise on one output and a low-gain amplifier to get the largest possible signal on another output. These two amplifiers are simultaneously read out and converted into digital values allowing both signals to be combined for a higher dynamic range image.
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2 comments:

  1. This was also done for CCDs, although the two amplifiers were off chip.

    I also found this for CMOS from 2001 Workshop.
    http://www.imagesensors.org/Past%20Workshops/2001%20Workshop/2001%20Papers/pg%20137%20YWang.pdf

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  2. While we are on the topic of high DR and sensitivity, can anyone confirm if Aptina and Advasense have signed a 2 year contract on the collaboration of 1.1um pixel sensors? Been hearing rumors of the 2 parties working on 8MP sensors using 90nm or 65nm node processes and fabbed at either TSMC or Micron on 12 inch wafers

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