Thursday, December 10, 2009

Omnivision High Full Well Photodiode

Omnivision patent application US20090302358 discloses a technique to increase the photodiode full well capacity in 4T pixel. The proposal is to reduce a transfer gate sidewall spacer closest to the photodiode, as shown on the figure below:

One may ask how this increases the full well of photodiode? Here is the explanation:

In the conventional process for fabricating a CIS, after the gate layer has been formed, the PD region is implanted next to the gate of the transfer transistor. After the PD region is implanted, but before the sidewall spacers of the transfer transistors are formed, the pinning layer is implanted. This order of fabrication provides pinning under the sidewall spacers, which helps to reduce dark current and white pixels. However, the thermal processing for sidewall spacer formation also causes the P type dopants of the pinning layer to diffuse, resulting in a less abrupt p-n junction and therefore a lower full-well-capacity.

In the Omnivision's proposal the abrupt junction of pinning layer is achieved by reordering the implanting pinning layer step to be after formation of sidewall spacers. To compensate for process reordering, thinned sidewall spacer is thinned relative to regular sidewall spacer. Sometimes the thinned sidewall spacer could be entirely removed.


  1. The Image Sensor World explanation is flawed -- a standard way to create the pinning layer is to implant it after the sidewall spacer in order to engineer the barrier between the photodiode and transfer gate. So the OVT patent moves the pinning edge closer to the gate edge, not farther.

    The tradeoff is well capacity versus lag -- moving the pinning edge away from gate edge increases well capacity, but makes problem of lag worse.

  2. First, the explanation is not mine, it's copied form Omnivision's patent application.

    Me too is saying Omnivision proposes to move pinning layer closer to the transfer gate, we are in agreement here.

    As for the stage when the pinning layer is implanted, I'm familiar with different process approaches, including the pinning layer implantation before and after spacers step. There are ways to control the barrier in both cases.

  3. As said in precedent comment, this type of thinned spacer may lead to LAG issue...especially with a high potential diode.
    Not sure to see what is so marvellous in this patent also !

  4. @ Not sure to see what is so marvellous in this patent also !

    Well, when looking through the recent patents I stopped at this seemingly bizarre claim that the full well capacity can be increased if transfer gate spacer is reduced. So I've read the application and thought that the explanation might entertain somebody else.

  5. From "Not sure to see what is so marvellous in this patent also !"

    Dear Image Sensor World, sorry didn't want to offend you ;o)


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