Image sensor blog from Japan puts together few words about Sony presentation at IEDM 2009 titled "0.9um Pitch Pixel CMOS Image Sensor Design Methodology".
As far as I was able to understand, Sony built 0.9um, 1.12um, 1.4um and 1.75um pixels using 0.18um FEOL and 65um copper BEOL process. All the pixels are FSI, rather than BSI. The pixels design was based on simulation results optimizing microlens shape, stack hight and metal opening.
1.1um pixel performance was considered OK. 0.9um pixel QE was unacceptably low. The article also mentions SNR10 being of order of 100Lux, not clear for what pixel size.