Tuesday, April 12, 2011

CMOSIS Announces its First Granted Patent

CMOSIS announces that on Feb. 1, 2011 the USPTO published its granted patent No. 7,880,662. This patent covers CMOSIS column parallel ADC as implemented in the the off-the-shelf image sensors CMV2000 and CMV4000 and several custom image sensor developments.

The patented ADC is of the counting ramp type combined with CDS in the digital domain and said to result in very low FPN. The prior art ADC with digital CDS has up and down counter to subtract the reset level from the signal level:


CMOSIS patented solution only needs a counting in one direction, while the subtraction is achieved by changing the timing logic. There are two version of counting logic presented:



Another advantage of the proposed ADC logic is that the full conversion can be achieved with just one analog ramp. In that case the comparator offset can be controllably changed between the signal and reset samples and the same counter can be used:


There are more techniques described in the patent, such as its application for TDI, pulse stretching or shrinking and clock interpolation.

9 comments:

  1. Changing counter direction with single slope for digital CDS is well known and can easily be demonstrated as a prior art.

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  2. True, changing the counter direction is prior art and it's clearly marked so. The patented idea is the counter without a direction change.

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  3. so what is the usefullness of this patent? Changing the counter direction is so easily... especially with their huge pixel pitch. So where is the problem? It's mainly marketing :(

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  4. Because one cannot use the prior art, would be a reason to invent something new. And while at it, prevent others doing exactly the same as you came up with, by patenting you idea. Regardless, this seems like an elegant solution, improving the prior art.

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  5. Here is a link to the patent:

    http://www.google.com/patents?id=Di3-AAAAEBAJ&printsec=abstract&zoom=4&source=gbs_overview_r&cad=0#v=onepage&q&f=false

    I'm wondering if the single slope ramp method will allow faster readout rates. If so then that's big plus.

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  6. so mainly to avoid potential problem with Cypress-Fillfactory...

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  7. I don't think the up-down patent is Cypress, I remember Sony (?) used to publish something with up-down counting ADC structure

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  8. Indeed Sony has prior art with up-down, we still have to see something on Cypress column ADC's.

    It seems that single slope ramp can go much faster, based on the specs of CMOSIS' CMV12000.

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  9. I know another patent for a counter without a direction change. This was filed by Sony. Which one is prior?

    http://www.google.com/patents/about?id=5R3OAAAAEBAJ&dq=US+2008/0224913

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