5 year-old CEA spin-off Asygn promises to break the speed barriers in the image sensor circuit simulation, allowing to simulate the whole image sensor circuit in reasonable time:
The company's Tactyle-MX simulator "has been used to simulate a 1.2M pixel imager device (where each pixel contained about 20 transistors) in less than 15 minutes on a basic machine using a single CPU." (The system time or accuracy numbers are not stated.)
"The most convenient way to understand the effect of pixel leakage or inter-pixel parasitics is to look at a sequence of complete images, comparing individual frames with each other and with references. Further, verification methodologies that do not include, at some point in the flow, a complete behavioural simulation based on the final netlist of a circuit run a considerable risk: if there are any errors in the extrapolation of results obtained on the test sub-circuits to the full device, then they may not be detected."
Examples of the effects that can be simulated:
The simulator is said to run on a real netlist, using the real, non-simplified, transistor models: