Tuesday, May 21, 2013

Asygn Image Sensor Circuit Simulator

5 year-old CEA spin-off Asygn promises to break the speed barriers in the image sensor circuit simulation, allowing to simulate the whole image sensor circuit in reasonable time:

The company's Tactyle-MX simulator "has been used to simulate a 1.2M pixel imager device (where each pixel contained about 20 transistors) in less than 15 minutes on a basic machine using a single CPU." (The system time or accuracy numbers are not stated.)

"The most convenient way to understand the effect of pixel leakage or inter-pixel parasitics is to look at a sequence of complete images, comparing individual frames with each other and with references. Further, verification methodologies that do not include, at some point in the flow, a complete behavioural simulation based on the final netlist of a circuit run a considerable risk: if there are any errors in the extrapolation of results obtained on the test sub-circuits to the full device, then they may not be detected."

Examples of the effects that can be simulated:

The simulator is said to run on a real netlist, using the real, non-simplified, transistor models:


  1. Have these guys ever designed any analog circuits really? It's non-sense to state 15mn for the simulation of 1.3M hyperactive pixels on a single CPU machine with no precision on the nature of the simulation.

  2. I wish to know more on how the electrical characteristics of the repetitive blocks are bundled to do a quick performance estimation at the array (full chip) level. This will also give an idea of the expected accuracy levels. Is there a technical paper on the technology?

  3. Hi all,
    Thanks for your reviews and comments.

    @Vladimir, Tactyle does not do transistors: it works with electrical behavioral models described with schematics from a primitive library (RLCs, switches, opamps, comparators and the like).

    @Anonymous, some more details on the quoted simulation: 1.3Mpix + column amps + 4 output video amps + row/col decoders. Pixels models include charge amp, reset switch, row select switch. Digital driven by VCD stimuli. Sequence of 2 pictures simulated.

    @Ankur, as models are used, you explicitly decide of the accuracy level (models are then solved with machine precision). This is different from other approaches like fastspice, where simplification is implicit. No technical paper so far, but some more details here:

    Also, if you happen to be at DAC this year in Austin, we're at booth 1241 with demos of this.

    Thanks again,

  4. Nicolas,

    Thanks for the information. Here is what I understand - Transistors are not involved in your simulations. Active circuit blocks are replaced by models (opamps, comps, etc.), and parasitics are added on top to represent the array level parasitics. Then, you do bandwidth, noise, etc. sims with such a full chip set-up.

    This could be a way to do full-chip functional verification checks, but not to estimate bandwidth sufficiency, noise, etc. Let me know if I am missing something.


  5. Ankur,

    You understood well. However, our customers actually use it both for functionality checks and performance checks. It really depends on how you model: if opamps are modeled with limited bandwith, you can check that bandwidth is sufficient. The same goes for noise (there is a transient noise generator primitive). Pixels do not have to be all the same: you can apply arbitrary distributions to model parameters and see the effect on the output images.

    Hoping this clarifies what we are doing.



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