GlobeNewswire: TowerJazz-Panasonic foundry (TPSCo) announces that it has qualified a 65nm CMOS image sensor interoperable process design kit (iPDK) for Synopsys’ custom design flow. The qualified iPDK complements TPSCo’s advanced 65nm CIS process technologies and provides support for Synopsys’ custom solution that includes; the Galaxy Custom Designer schematic editor and simulation environment, Laker layout editor, HSPICE, CustomSim and FineSim circuit simulators, IC Validator physical verification, and StarRC parasitic extraction.
TPSCo’s CIS technology is aimed to mobile, high-end photography, security, surveillance, medical and industrial applications. TPSCo’s 65nm 1.12um pixel process is said to have the world leading figures of merit, and is already in mass production for mobile camera applications.
“TowerJazz and Synopsys have been collaborating for many years to create and promote iPDKs to assist with the design and development of mutual customers’ innovative devices and we are pleased this partnership has been extended to TPSCo to meet the needs of our customers and address the increasing complexity of CMOS image sensor design,” said Tomoyuki Sasaki, CTO of TPSCo.
“The CMOS image sensor market is an ideal fit for Synopsys’ custom design solutions,” said Bijan Kiani, VP of product marketing at Synopsys. “Through close collaboration with TowerJazz Panasonic Semiconductor Co. on iPDK development, we are able to expand our offering in the CIS market and ensure that our mutual customers have access to a qualified solution that provides increased custom design productivity.”
Update: TowerJazz-Panasonic has a nice technology page explaining its 1.12um pixel advantages:
Other production-ready pixel offerings are in the table below: