Tuesday, June 16, 2015

More Details on Sony Fast Full-Frame and 1-inch Sensors

Imaging Resource publishes an interview with Kimio Maki, Senior General Manager, Digital Imaging Business Group, Sony, discussing various trade-offs in image sensors for A7R II full-frame camera and RX100 IV and RX10 II 1-inch compacts. Few interesting points, in no particular order:

  • Why Sony needs a backside illumination in its new 42MP FF sensor:
    (a) to match a pixel sensitivity of its earlier 36MP front side illuminated sensor
    (b) to be able to use metal routing more freely, without obscuring the light path
    (c) better metal routing, together with Cu instead of Al in the previous sensor allows to implement 4K video mode in that big sensor
    (d) the new sensor is 3.5x faster than the previous generation one
  • 42MP resolution has been chosen to ensure an easy image scaleability in various 4K video modes. If not that, Sony marketing would prefer 45MP or 50MP resolution.
  • Other than the speed, Sony has improved the noise performance in the new FF 42MP sensor over the older 36MP one.
  • The 14b raw file format suggests that 14b ADCs are used on the new FF sensor
  • The new 1-inch stacked sensor is 5x faster than the previous one
  • The fast readout speed creates close to global shatter experience, although the shutter is actually rolling. Sony calls is "Anti-Distortion Rolling Shutter."
  • To get to that high speed, the 1-inch stacked sensor employs no less than 16 ADCs per column (!)
  • Since the 1-inch sensor has 5,472 columns, the number of column-level ADCs is  87,552
  • The data from ADCs is transferred to the bottom DRAM die and, then, outside of the chip
  • The DRAM die also has a "low level" processor integrated on it

Sony 1-inch stacked sensor assembly. The chips are inverted
and connected to the bottom of the sensor package using some
sort of solder-bump technology.


  1. 16 ADC per column.. wired how? 16 read lines per column, each one contacted every 16 pixels?

    16 segments will lead to tearing when panning. Or a single read line with 16 sample-holds?

    1. I guess we need to wait for the next Sony ISSCC paper.

    2. It's possible, since this is a BSI sensor. Suppose that they a fine metal pitch of 0.2um (0.1um+0.1um), then 16 column lines will take 3.2um. The ADC counters are on the lower CMOS chip and 16 counters per column are possible.


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