Monday, June 29, 2015

IFTLE on Stacking Technology Progress

Insights From Leading Edge blog overviews image sensor stacking progress and recent publications. "Given the continued, aggressive stacked CIS development underway from independent device manufacturers (IDM) and foundries it’s predictable that stacked chip adoption will occur very rapidly over the next few years."

Sony ISX014 Stacked dice (Chipworks)


  1. Just to understand the very basic principle, without being interesting in details...: how can the stacking be done? Do they bond entire wafers on top of each other? The interconnect must be something different than a soldering process. Can the contact positions be prepared in a way that adhesion force does the bond?
    -- Thomas

    1. See

      Sony also extended their Ziptronix licensing to DBI very recently. That gives them up to 100,000,000 electrical connections per square centimeter (1.6 micron pitch has been demonstrated -- one connect per pixel-ish).

      Zibond is done cold (anneal to T < 250C) and covalently bonded. No adhesives or other additives.

      They can either bond die to a wafer or wafer to wafer.

      The vias line up and contact using the force of the bonding between two silicon wafers/dice.


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