Friday, March 04, 2016

Brillnics Patent Applications Published

Many have been wondering what Junichi Nakamura's startup Brillnics is working on, especially after TSMC pixel group head S.G. Wuu has joined them. Two PCT patent applications might shed some light on it:

WO2016009942: SOLID STATE IMAGING DEVICE, METHOD FOR PRODUCING SOLID STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS by TAKAYANAGI, Isao; TANAKA, Shunsuke; MORI, Kazuya; ARIYOSHI, Katsuhiko; MATSUO, Shinichiro.

WO2016009943: SOLID-STATE IMAGING DEVICE, METHOD FOR PRODUCING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS by AKAYANAGI, Isao; TANAKA, Shunsuke; MORI, Kazuya; ARIYOSHI, Katsuhiko; MATSUO, Shinichiro.

While the detailed description is in Japanese, just from the abstract and figures, it appears to be a stacked sensor built on CMOS pixel with CCD-like charge transfer and storage:

"This solid-state imaging device 100 has: a light sensitive unit that includes pixel units 211, which are disposed in a matrix, and charge forwarding units 212 for forwarding, by the column, the signal charge of the pixel units; a plurality of charge accumulation units 220 that accumulate the signal charges forwarded by the plurality of charge forwarding units of the light sensitive unit; a relay unit 240 that relays the forwarding of the signal charges forwarded by the plurality of charge accumulation units to each charge accumulation unit; an output unit 230 that outputs the signal charges of the plurality of charge accumulation units as electric signals; a first substrate 110 at which the light sensitive unit 210 is formed; and a second substrate 120 at which the charge accumulation unit 220 and output unit 230 are formed. The first substrate and second substrate are laminated together, and the relay unit 240 electrically couples the charge forwarding unit of the first substrate to the charge accumulation unit of the second substrate by means of a connection section traversing the substrates outside the light sensitive region of the light sensitive unit."


The most interesting part is a charge transfer between the stacked dies through TSV:

7 comments:

  1. This idea is similar to Lincoln lab's hybride CCD.

    -yang ni

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  2. Does anybody have an idea about how they intend to solve the reset noise issue of the non-depleted n+-TSV node?

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    1. I'm not sure how Brillnics solves this, but I would propose a number of ideas:

      1. Implement an active MOSFET-based CDS circuit on the top die and amplify the signal after that. Then, the kTC noise would be reduced by the amp's gain factor.

      2. Transfer the signal as is, with kTC noise, and then measure the residual TSV potential after the charge transfer is complete. The measurement value difference from the previous pixel transfer (which is initial value for the next transfer) represents the kTC noise. What we do with it is another matter. For example, we can amplify it and inject as an additional compensating charge into the bottom die CCD chain. This kTC compensating circuit can be entirely implemented on the bottom die.

      3. The top die pixel might already have amplification, so that when the signal is injected into the top CCD, it's already amplified well above the kTC noise level. In fact, their pixel structure is not clear to me from the patent app.

      What I like about Brillnics approach is a very high speed they can achieve even in large arrays. If they can clock their CCD at 50MHz, they can get 20ns per row readout. For a 15,000 x 10,000 150MP pixel array, it would mean 5,000fps, crazy fast. It's frightening to think about their power consumption, though.

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    2. Vladimir, I think that this could be a way to overcome the 1/f and RTS noise in CMOS pixels. A parallel readout can reduce considerably the bandwitdh of the CCD readout and get very low noise. The work at Lincoln lab used an Indium bump approach to do this and got very low noise electron number...

      -yang ni

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    3. Thanks for sharing your ideas!

      @Vladimir: your point 1 - as well as Yang Ni's comment - seem to refer to an active top die. Looking at their cross-sections, to me it seems that is exactly what they aim to avoid though!? Your point 3 also either points in this direction or into charge-level amplification (avalanche gain? - this would also increase noise somewhat...).

      I'm not sure whether I fully understand your point 2. And to be honest, I don't get the above sketches either. The way I understood this is that the TSV-node should be an almost infinite source of electrons. That means that one would not manage to get the surface potential of P3 low enough to yield full charge transfer from the TSV node as it is seemingly indicated in the timing diagrams above. (They have one comment on this particular region, but, unfortunately, I don't speak Japanese - can anyone please clarify?) Thus, I'd assume to end up with lots of noise.

      Measuring the kTC noise at the TSV as you proposed it could indeed be a solution. Only drawback - the sense-node cap is probably poor here, no? Thus, I wouldn't expect a good noise performance either...

      I think I saw a similar patent application by Apple within the last year highlighted on this blog where they also proposed charge transfer through an n+-metal-n+ interface. How did they solve this? Also this looks similar to the fat zero approach in CCDs, no? I'd really appreciate a comment of one of the CCD gurus... Albert? :-D

      With the limited insight I have so far, to me it seems having an active top layer would still be preferable over charge transfer through such an interface... but please prove me wrong!

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    4. Andreas, I completely agree with you that in the form as it's described in the patent there is kTC noise on TSV node. I just tried to propose some ways to fix it.

      In #2 proposal, one can measure the remaining voltage on TSV. Ideally, if the TSV charge happens to be fully transferred, the TSV voltage upon the end of each transfer cycle stays the same. In reality, due to the kTC noise and other effects, TSV voltage changes from one cycle to another. One can sample this difference and calculate the residual charge that stays on TSV node. Then, once the noise is measured, one can compensate it by, for example, adding it to the bottom die CCD somewhere down the signal line. Hope this explains my #2 proposal better.

      I agree with you that TSV capacitance is not small, and thus kTC noise can be high.

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    5. Thank you! Indeed our thoughts seem to be aligned. Btw. my comment regarding the large TSV cap didn't only point towards kTC noise. You said that you want to measure the TSV potential. That means you're basically using this node for a charge-voltage conversion, which in this case can also be somewhat noisy due to the large cap./low conversion gain. However, as this seems to be done only once per column, I guess there should be enough space for a decent low-noise amplifier...

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