Monday, April 02, 2018

Quanta Image Sensor Lecture

University of Illinois publishes Eric Fossum March 29, 2018 presentation on QIS:

" The Quanta Image Sensor (QIS) is a possible 3rd generation solid-state image sensor technology based on photon-counting. Primarily focused on scientific and defense applications, it may also be useful for consumer applications. The specialized QIS pixel device and its deep sub-electron read noise will be discussed. The specialized pixel uses ultra-low capacitance rather than avalanche multiplication to achieve single photoelectron detection capability. The high frame rate, low power readout will also be described. The QIS opens new possibilities for computational imaging.

6 comments:

  1. Nice presentation - a layperson like me could actually follow it.
    Would have liked some estimate on difficulty of scaling from one million to one billion jots, and clever ways of dealing with colour beyond the one suggestion. And possibly a comment on whether big players in sensor manufacture are on the ball.

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  2. Thanks Prof. Viktor Gruev for the kind invitation. I am happy with the way this talk went although I forgot it was being recorded. Sorry the QIS part got a little rushed at the end. @Jonas - Cluster parallel is great for scale up so scale up issue is shrinking jot size a bit, and power is 18mW/Mjot incl pads now so 1000x=18W is 10x too much. Should be ok with tech node scaling. Pad count is also an issue for parallel output.

    Question for the community - do students care about history of image sensors? Their parents may have been born the same time as the CCD so ancient history. Perhaps only aging professors care about such technology history. What do you think? Should I keep it in my standard talk?

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  3. Not directly related to the talk, but the CCD introduction brought this back to my attention: One of the main features of CMOS over CCD is the ability to integrate ADC, TG, etc. on die. Ironically, state of the art sensors have two dedicated dies, bonded together, again. How would a CCD die bonded to a second die with ADCs and digital stuff compared to this? The horizontal shift register could be skipped with column parallel ADCs.

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    1. I have been thinking about this (again) for a few days. Twenty years ago (May 1998 IEEE Micro) I wrote this. I think it is still true, but for TDI in high-priced camera systems your "throwback" suggestion probably has merit.

      "The great battle between CCDs and CMOS APSs is just beginning as CMOS
      APSs begin to not only open new markets but also absorb market segments previously controlled by CCDs. CCD manufacturers can be expected to counter with cost reductions (as has already begun) and with lower power requirements. While CCD cameras could, in principle, be shrunk to two-chip solutions (CCD plus a do-all CMOS chip), improved functional capabilities and low-power advantages are fundamental to CMOS-based imaging technology. The next five years will be interesting times indeed."

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  4. Hi Eric, thanks for the very interesting speach. One point I maybe missed - whats the intended interface to the "outside world"? Will there be a datareduction already in the stacked 'logic layer' or will there be a broadband interface to a next step device like FPGA?

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    1. I expect there will be data reduction in the stack, but I also think it will be application-specific. Right now we are focused on the basic detection and "internal" readout. The current prototype puts out 1Mpixel at 1040 fps or about 1Gb/s which is manageable but even now, data reduction would be convenient for even lower power (currently 20mW incl pads) and smaller form factor (pad count).

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