Wednesday, April 22, 2009

TSMC Keeps Investing in CMOS Process Development

EETimes UK reports that TSMC is developing a new CMOS image sensor process for 2-, 5-, and 8MP designs, despite it already has a new 0.11um process.

TSMC also develops 3D process extensions. By June, it will ready its 300mm fab for TSV applications.


  1. BSI and TSV? Why bother? Maybe the TSV is for some other application?

    As far as going to 0.11um, maybe they need the smaller line size to make 1.4 pixels work properly?

  2. You are right, TSV can be used in a number of applications, not only in image sensors. As for 0.11um, it sounds like TSMC is investing in development of the next generation smaller geometry process, but it's not clear for what pixel size.

  3. Out of curiousity why are you so negative about BSI, Anonymous?

    TSV will be of vital importance in high speed processors/memory subsystems in coming years. The transition from multicore to many-core will require a huge increase in bandwidth delivered to the processor and conventional packaging will not permit such a large number of signals to be supported in a practical way (in the range of 10,000 signals needed between the processor die and the tertiary cache die). TSV and stacking is the only practical way to support that.

  4. Out of curiousity why are you so negative about BSI, Anonymous?

    I'm not really negative on BSI, I just haven't seen it from anybody but Sony. Looks like OV wants to do it cheap for the mass market, but OV has announced technical breakthroughs like TrueFocus that have yet to be seen in the market place. I realize these things take time, so I'm just erroring on the side of caution.

  5. It seems necessary to use BSI if you want to sense UV with a CMOS sensor; otherwise don't you lose nearly all the energy to the wiring and dielectric layers?

  6. To maintain constant pixel SNR (say 10) at some lux level (say 100) with shrinking pixel sizes, we need to increase the number of photons that we you utilize. BSI helps increase the photon utilization beyond what one achieves with microlenses and also avoids some other problems.
    I believe most companies chasing small pixels are also heading down the BSI path.

    (at some shrink point, relatively soon, there are not enough photons available at 100 lux to maintain an SNR of 10, even if you absorb and collect them all, depending on the f-no)

    I guess by losing energy you are asking about losses due to absorption? BSI relies on thinning the backside so that the absorption of photons takes place in the silicon near the "wiring and dielectric layers".



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