Wednesday, October 30, 2013

Sony Applies for GS Pixel Patent

Sony patent application US20130277535 "Solid-state image sensor and electronic device" by Takeshita Kaneyoshi and Nomoto Kazuki presents two CCD-like structures to implement CMOS GS pixel:


  1. Guess this is going to need some claims work. CMOS APS with FG was done by Junichi Nakamura and me and published in IEEE TED Sept 1995 which wipes out several claims. A multi-stage CCD in the pixel is claimed in some of the earliest JPL/Caltech patents (which Sony has probably licensed already) and specific structures like that for GS were also claimed. BTW, FG-type CMOS APS works fine, but not as fine as PPD and FD. Lots of biasing issues with FG, esp. with lower voltage rails.

  2. Does GS mean gain-switched? And is the mechanism that switching the transistor at 25 changes the capacitor value? And, does that mean the pixel probably couldn't do dual high-gain/low-gain readout?

    1. M25 looks like floating gate reset to me. The gain is related to the cap of the FG node when floating, along with the cap to substrate. It is sort of a capacitor divider network, but transferring charge under FG changes the potential on FG and that is what is sensed. Switching in more cap to reduce the gain is easy so you could do that if you wanted too.
      FGs are traditionally used in multiple non-destructive read devices (distributed floating gate amplifier, for example) yield low noise by old CCD standards and I think in some CID-like image sensors. It was also proposed for multiple read CMOS APS for noise reduction in the very early days by our group at JPL. All in all, I don't see it as being particularly useful these days but perhaps Sony has something up their sleeve.


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