Electronic Imaging 2014 program has been published and has many nice image sensor papers. An incomplete sample of them is below:
A statistical evaluation of effective time constants of random telegraph noise with various operation timings of in-pixel source follower transistors
Akihiro Yonezawa, Rihito Kuroda, Toshiki Obara, Akinobu Teramoto, Shigetoshi Sugawa, Tohoku Univ. (Japan)
"RTN (Random Telegraph Noise) causes the image degradation in CMOS image sensor (CIS). At readout operation in CIS, the row selected pixel-SFs (source follower) turn on and not selected pixel-SFs operate at different bias conditions depending on the select switch position. In this work, we extract RTN time constants and amplitude with various pixel-SFs duty ratios and cyclic periods statistically. Some MOSFETs have RTN in different duty ratios. However other MOSFETs with RTN do not observed in different duty ratio. For MOSFETs which have large RTN amplitude in different duty ratios, the MOSFETs with RTN have almost the same RTN amplitude. It is considered that the RTNs of same MOSFET in different duty ratio caused by same oxide trap. The scatter plot of average time constant ratio (<τc> / <τe>) of different duty ratio widely distributed. Especially, when duty ratio = 1, the distribution of <τc> / <τe> at duty ratio = 1 tend to be smaller than that of <τc> / <τe> at duty ratio =7.1 times 10^-3. The probability of capture and emission of the carrier changes depending on the pixel-SF operation duty ratio. These results are important for the detection and analysis of in pixel-SF with RTN."
Pixel structure with 10 nsec fully charge transfer time for the 20M frame per second burst CMOS image sensor
Ken Miyauchi, Tohru Takeda, Katsuhiko Hanzawa, Yasuhisa Tochigi, Shin Sakai, Rihito Kuroda, Tohoku Univ. (Japan); Hideki Tominaga, Ryuta Hirose, Kenji Takubo, Yasushi Kondo, Shimadzu Corp. (Japan); Shigetoshi Sugawa, Tohoku Univ. (Japan)
"In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In the 30.0 umH X 21.3 umV fully-depleted pinned photodiode (PD), the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending the edges of the semicircular regions. To create an electric field greater than average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. We designed the PD structure, which included the n-layer shape and the PD dopant profile with the condition of three times n implantation, and the TG structure. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed two key characteristics as follows; firstly, the entire PD area had sensitivity. Secondly, image lag was below the measurement limit."
Novel CMOS time-delay summation using single-photon counting for high-speed industrial and aerospace applications
Munir M. El-Desouki, King Abdulaziz City for Science and Technology (Saudi Arabia)
"Time-delay integration (TDI) is a popular imaging technique that is used in many applications such as machine vision, dental scanning and satellite earth observation. One of the main advantages of using TDI imagers is the increased effective integration time that is achieved while maintaining high frame-rates. Another use for TDI imagers is with moving objects, such as the earth's surface or industrial machine vision applications, where integration time is limited in order to avoid motion blurs. Such technique may even find its way in mobile and consumer based imaging applications where the reduction in pixel size can limit the performance during low-light and high speed applications. Until recently, TDI was only used with charge-coupled devices (CCDs) mainly due to their charge transfer characteristics. CCDs however, are power consuming and slow when compared to CMOS technology and are no longer favorable for mobile applications. In this work, we report on novel architectures that use single-photon counting based TDI techniques that are implemented in standard CMOS technology allowing for complete camera-on-a-chip solutions. The imager was fabricated in a standard CMOS 150 nm 5-metal digital process from LFoundry."
Pixel structure for asymmetry removal in ToF 3D camera
Byong Min Kang, Jungsoon Shin, Jaehyuk Choi, Dokyoon Kim, Samsung Advanced Institute of Technology (Korea, Republic of)
"Most of time-of-flight (ToF) cameras have a two-tap pixel structure for demodulating a reflected near infrared (NIR) from objects. In order to eliminate the asymmetry between two taps in the pixel, a ToF camera needs another measurement, which collects photo-generated electrons from reflected NIR by inverting the phase of clock signals to transfer gates. This asymmetry removal needs additional frame memories and suppresses the frame rate due to the additional timing budget. In this paper, we propose novel asymmetry removal scheme without timing and area overheads by employing 2×2 shared two-tap pixels with cross-connected transfer gates. The 2-tap pixel is shared with neighbor pixels and transfer gates in the pixel are cross-connected between upper and lower pixels. In order to verify the proposed pixel architecture, we designed the prototype sensor chip and the camera system, which generates color and depth images alternately.. The sensor with cross-connected transfer gates has 1280×960 pixels (640×480 with 2×2 binning), which has been fabricated using 0.11 μm CMOS process. The camera system mounting the sensor chip uses 16 MHz modulation frequency, f/1.6 lens, NIR LED array with 850 nm, and 20 msec integration time."
Review of ADCs for imaging
Juan A. Leñero-Bardallo, Jorge Fernández-Berni, Ángel B. Rodríguez-Vázquez, IMSE-CNM (Spain), Univ. de Sevilla (Spain)
"The presentation will be focus on ADCs for imaging. We will describe the state-of-the-art and discuss the special specifications that ADCs for vision sensors must satisfy. Firstly, we will establish what are the ADCs requirements for modern imaging: number of bits, area, fix pattern noise, and power consumption. We will discuss how some of these specifications can be relaxed, depending on the application, to save power or area consumption. We will review briefly the main ADCs topologies employed for imaging nowadays: SAR, cyclic, slope, and SD. Their advantages and disadvantages will be discussed. Their limitations depending on the desired frame rate, the required conversion speed, and area consumption will be explained. Examples of how a bad design of an ADC for imaging can degrade image quality will be shown. Thirdly, we will mention the most relevant recent publications. Their performance will be compared based on a FOM. The main trends in ADC for imaging will be presented. Some design considerations for future ADC integration in 3D technologies will be explored. Finally, we will draw some conclusions about the current and future trends of ADC design for imaging. We will conclude justifying the need of designing specific ADCs for imaging."
A high fill-factor low dark leakage CMOS image sensor with shared-pixel design
Min-Woong Seo, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito, Shizuoka Univ. (Japan)
"We have proposed and evaluated the high-responsivity and low dark leakage CMOS image sensor with the ring-gate shared-pixel design. A ring-gate shared-pixel design with a high fill-factor makes it possible to achieve the low-light imaging. As eliminating the shallow trench isolation (STI) in the proposed pixel, the dark leakage current is significantly decreased because one of major dark leakage sources is removed. By sharing the in-pixel transistors such as a reset (RT), select (SL) transistors and source follower (SF) amplifier, each pixel has a high fill-factor of 43 % and high sensitivity of 144.6 ke-/lx•sec and its conversion gain is a 22.9-μV/e-. In addition, the effective number of transistors per pixel is 1.75. The proposed imager achieved the relatively low dark leakage current of about 104.5 e-/s (median), corresponding to a dark current density J [proposed] of about 30 pA/cm^2. In contrast, the conventional type test pixel has a large dark leakage current of 2450 e-/s (median), corresponding to J [conventional] of about 700 pA/cm^2. Both pixels have a same pixel size of 7.5×7.5 μm^2 and are fabricated by a same process."
A CMOS time-of-flight range image sensor using draining only modulation structure
Sangman Han, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito, Shizuoka Univ. (Japan)
"This paper presents new structure and method of charge modulation for CMOS TOF range image sensor using pinned photodiodes. Proposed pixel structure allows us to achieve high-speed charge transfer by generating lateral electric field from the pinned photo-diode (PPD) to the pinned storage-diode (PSD). And generated electrons by PPD are transferred to the PSD or drained off through the charge draining gate (TXD). This structure allows us to realize a trapping less when the charges transfer between PPD and PSD. Therefore, it can reduce the noise that is caused by a transfer gate (TX). The pixel consists of a PPD, a PSD, a TXD, a TX for readout between the PSD and the floating diffusion (FD) with MOS capacitor for increasing the full well capacity, a reset transistor and a source follower amplifier transistor. A TOF range imager prototype is designed and implemented with 0.11um CMOS image sensor. The accumulated signal intensity in PSD as a function of the TD gate voltage is measured. The ratio of the signal for the TD off to the signal for the TD on is 33:1. And the response of the pixel output as a function of the light pulse delay has been also measured."
Thanks to AT for giving me a heads-up!