Friday, March 28, 2014

Aptina Proposes Backside PD

Aptina's patent application US20140077062 "Back side illuminated image sensors with back side charge storage" by Jaroslav Hynecek describes an unusual pixel idea - move the PD implant to the backside:


The advantages of such an approach are not clear to me, but it's a fresh idea and can work, if pixel is not too small and one can spare 10-20V to control the transfer gate Vtx.

10 comments:

  1. Not so fresh. This is pretty much what I described as a "Vertical Charge Transport" device during my 2011 IISW talk on the two-layer structure, using the old CCD vertical shutter concept (so doubly not so fresh). The difference being that I had a storage well both on the front and backside to accomodate storage of two "colors" (yellow and blue, resp.), with sequential readout.

    I don't think Samsung ever pursued a patent on the concept and it was never reduced to practice. Not sure if a slide presented at the 2011 IISW would count as prior art, and Jerry wasn't even there to see it. Guess it was not so memorable....

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  2. Assuming IISW 2011 was a public event (pretty sure it would be considered public), then yes, any slides presented at it are considered prior art.

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  3. Beets chip stacking. All the circuits on front and only the PD at the back. this is 100% aperture and charge storage efficiency.

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    1. I think that is mostly true with any BSI technology.

      Making this device would be challenging. It requires good backside p+ and deep implants to reach the backsurface. Also, frontside dark current is not suppressed according to this figure.

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    2. the backside N- & P+ layers could be made with epitaxy. Frontside DC should be able to be reduced by surface pinning.

      -yang ni

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    3. Last time I checked, epitaxy would exceed the thermal budget for maintaining front side structures incl. metallization. (exception being the old, expensive,JPL process). I think low energy implant followed by a quick anneal is the current BSI technique but others know better. The diagram shows frontside "pinning" but this seems to be inaccurately drawn. Implanted pinning (usual) will still leave the frontside pinned during vertical charge transfer. It has to be dynamically pinned. Jerry understands this all quite well, as father of the VP CCD. I am just saying fab will be challenging.

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  4. QE is perhaps the same for any BSI, but charge storage is certainly better at the back side than on the front side. The back P+, N+ can be made by implants and laser anneal as is typically done. Perhaps also MBE would work as JPL is doing on some sensors now.

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    1. QE is not the same for any BSI, esp in the shorter wavelengths, but maybe it is not a big difference in blue. Why do you think charge storage is "certainly better" at the backside?

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    2. It seems that the charge storage area can be almost the same as the pixel size and nothing is taken away for any transistors and the transfer gates. It seems that from this point of view this approach may be better than the chip stacking. Perhaps it is the PoBo (poor boy) chip stacking.

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    3. Yes, the apparent fill factor for the SW is better on the backside. But the deep isolation implants take some space due to straggle at a 3 um implant depth so the full pixel area is not available. More importantly is the capacitance of the SW. Too much doping concentration in the SW and you will have trouble transferring the charge with reasonable voltages. I imagine the practical capacity will be less than frontside, even considering the fill factor. With simulation one would know for sure, but it certainly is not "certainly better."

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