Monday, August 13, 2012

ESPROS Offers Open Interview

Enrico Marchesi, Head of Marketing & Sales at Switzerland-based ESPROS Photonics image sensor foundry, offered a unique opportunity to answer on our questions about the company and its technology. It would be sort of open interview when everyone of us can ask questions, as many as we wish. Then Enrico will filter out the offensive questions and also those that ask for a too sensitive information, and present his answers on the rest of them.

One can read about ESPROS foundry offerings on the company's website (click on side links there). ESPROS internal work on ToF images has been covered in this blog here and here.

Please feel free to submit questions in comments.

15 comments:

  1. What's the process for submitting questions - just post to this ISW comment section?

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    1. Yes, I meant to submit in comments. Sorry if this was not clear, I've just added it to my post.

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  2. ESPROS has their own process and they want to build their own fab inside a Swiss mountain. What is the status of creating the fab? Where are the chips currently manufactured until the mountain fab is not in full production?

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  3. A true "opto" foundry is a compelling offer for potential research partners, but all relationships will need to be long term affairs. How long is the company funded for currently? And when does ESPROS expect to be profitable?

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  4. I think that they are following the same mistake of UMC. A foundry should be a pure-foundry without their own products. Otherwise, it's hard to capture real business. The financier should make the design/product team spined off from the foundry as an independant FAB less company.

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  5. Thanks for your posts so far. Please keep going as I will wait for a couple of days to collect your questions. I will come up with less frequent but longer answers.

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  6. Do you plan to provide your backside processing steps also to customers with their own silicon from other fabs?

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  7. On the technical front (with apologies if this is outside the remit of this discussion):

    What implications does the ESPROS process have on achievable fill-factor for sophisticated APS-cells with >100 transistors? Do BSI photodiodes extend beneath active circuitry?

    Do you (or will you) have montecarlo models for your foundry transistors?

    Are 3-colour filters a possibility?

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  8. 1. Could we get more information on the epc660 chip? Some details on power consumption, ADC speed and resolution, pixel full well, pixel noise floor, pixel fill factor, pixel cut-off frequency, number of transistors per pixel etc. would be appreciated.

    2. Is it possible to shrink the pixel size further below a 20um pitch? What is the smallest reasonable pixel size you would expect in this process? What are the limiting factors?

    3. Which of the building blocks used in this chip (ADC, pixel, opamp, ...) are part of the design kit that any process customer may use?

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  9. 1. Do you have a 4T pixel process available? If yes, what is the qualification status of that process?
    2. Are ESPROS fab engineers open for discussions on tweaking the process? E.g. doping levels, doping energy's, accepting violations against PDK.
    3. What would be the standard cycle time for fully processed wafers?
    4. Which pixel sizes do you support?
    5. Is the backside thinning done internally or do you work with a partner?

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  10. Have you developed SPADs? If not, is it included in your roadmap?

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  11. Wah! The wish list is long...

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  12. Thanks for your questions so far. Here's the first set of answers. Multiple posts due to size restriction per post.

    Q: ESPROS Photonic CMOS™ Process
    Our ESPROS Photonic CMOS™ Process is a proprietary process that was developed by epc. The focus for this development was on the specific needs of industrial and scientific applications. We combined three core requirements in order match the respective market needs: Maximal near infrared sensitivity, CMOS digital/analog signal processing, high performance CCD imaging.
    One key aspect is the backside illumination. The BSI concept of epc’s optical detectors yields the major advantage of a 100% fill factor.
    epc has set up the full fabrication flow to handle thin dies from wafer level, comprising testing, bumping, dicing, sorting & picking. On top of that, we have been able to show with our development partners that these bare die CSPs can be handled on an industrial scale SMD production line by soldering the chips directly on a standard PCB.

    Q: The Fab / Production Capabilities
    It is our defined goal, to build the complete chip manufacturing chain here in Switzerland. Currently, we are working with external partners who cover some parts of this chain. However, it is important to state that our partners have fully implemented our proprietary process steps. Our own manufacturing is constantly being expanded.

    Q: Why do we develop our own products?
    A justified question and an important business decision. The reasons are manifold.
    First, it's based on time-to-market considerations. Our complete process package differs substantially from current fab offers. The time to provide a complete, ready to use design and manufacturing offer to the market from scratch requires substantial work in many fields. Unless the process is fully developed and qualified and all the necessary tools and processes along the complete supply chain are developed and implemented no sales are generated. Do the math ;-)
    Second, designers that are new to our process environment need some time to accommodate with the new options and approaches we offer. And we need to offer active support in order to get them going. Again, more time needed, before sales are generated.
    Third, the specific performance of our technology allows for somewhat new solution approaches in different markets. Our analysis of these markets made us decide to actively enter these market with products.

    Q: Do you plan to provide your backside processing steps also to customers with their own silicon from other fabs?
    I am not sure if I get the question correctly.
    But the combination of our specific backside processing with other CMOS or CCD processes does not make sense. The backside process is an inherent part of the complete process. Applying it to standard wafers would probably just destroy them …
    If you were asking on a more general level then it looks different: By now, we have acquired a certain competence in wafer backside processing. If a customer requires such knowledge and the associated manufacturing capabilities we are totally open for discussions.

    Q: Information on the epc600 TOF chip?
    I regret, but at this point we cannot disclose further information on this device. I can just ask for your patience. However, we will soon release the epc600 TOF Range Finder and the epc610 TOF Imager and the respective data sheets.

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  13. Q: What implications does the ESPROS process have on achievable fill-factor for sophisticated APS-cells with >100 transistors? Do BSI photodiodes extend beneath active circuitry?
    If certain precautions are taken, the fill factor will stay up to 100% even with pixels having complex internal circuitry. Our process makes the silicon under the circuitry optically sensitive in a controlled manner. We have already realized pixels with ca. 40 active components at 100% fill factor.

    Q: Are 3-color filters a possibility?
    Yes, these are certainly possible. But we have not put any emphasis on the respective development as our IR operating range and the associated applications have not required that so far. And BTW: microlenses will not be necessary for our APS's due to the 100% fill factor, resulting in a large degree of freedom freedom for the lens designer.

    Q: Do you (or will you) have montecarlo models for your foundry transistors?
    Currently, we have montacarlo models available for the low voltage devices. The model is constantly expanded.

    Q: Have you developed SPADs? If not, is it included in your roadmap?
    No and no

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  14. TSMC has a testing division of more than 50 persons working on pixel sensor development, but they don't have any own products.

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