Talking about the IO speed, 25GPixel/s limitation is somewhat obsolete by now. For example, PCIe 4.0 standard defines 32 lanes of 16Gbps each, with the aggregate bandwidth of 512Gbps. Assuming 10b per pixel, one can get 51GPixel/s I/O speed by just buying the PCIe 4.0-compliant IP. And PCIe 4.0 is not the fastest interface these days.
I think that the 300Gbs refers to the physical limitations of a single lane of Cu interconnect. The PCIe standard you are referring to achieves that via redundancy, and is in reality 20x below the physical limit of Cu
ReplyDeleteFirst, PCIe 4.0 is fairly conservative with respect to the speed per lane. There are faster interfaces, such as 28Gbps and 32Gbps per lane on the market, and 56Gbps and 112Gbps per lane are in development.
DeleteRegarding the 300Gbps Cu "physical limitation", I'm not sure what you refer to. It definitely depends on the type of the lane - whether it is on PCB or interposer, the type of PCB and interposer, trace length, and many, many other parameters. In most of these cases, the speed can go much faster than 300Gbps per lane. The practical power would limit us well before than the theoretical speed.