Thursday, October 06, 2016

Image Sensors at IEDM 2016

IEDM 2016 to be held on December 3-7, 2016 in San Francisco publishes its agenda with many image sensor papers:

8.1 Backside Illuminated SPAD Image Sensor with 7.83μm Pitch in 3D-Stacked CMOS Technology,
T. Al Abbas, N. Dutton*, O. Almer, S. Pellegrini*, Y. Henrion* and R. Henderson, The University of Edinburgh, *STMicroelectronics

We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both intensity, and time-resolved imaging. The 128x120 prototype has a 7.83μm pixel pitch with 45% fill factor. A 40nm bottom tier hosts the processing electronics while a 65nm top tier hosts the photo-detectors.

8.2 256×256, 100kfps, 61% Fill-factor Time-resolved SPAD Image Sensor for Microscopy Applications,
I. Gyongy, N. Calder, A. Davies*, N. Dutton**, P. Dalgarno*, R. Duncan*, C. Rickman* and R. Henderson, University of Edinburgh, *Heriot-Watt University, **STMicroelectronics

A 256×256 Single Photon Avalanche Diode image sensor operating at 100kfps with 61% fill factor and 16µm pixel pitch is reported. Gating and cooling allow the suppression of dark noise, which, together with the high fill factor, enables competitive low-light performance with electron multiplying CCDs whilst offering time-resolved imaging.

8.3 An APD-CMOS Image Sensor Toward High Sensitivity and Wide Dynamic Range (Invited),
M. Mori, Y. Sakata, M. Usuda, S. Kasuga, S. Yamahira, Y. Hirose, Y. Kato, A. Odagawa and T.Tanaka, Panasonic Corp.

8.4 Novel Stacked CMOS Image Sensor with Advanced Cu2Cu Hybrid Bonding,
Y. Kagawa, N. Fujii*, K. Aoyagi*, Y. Kobayashi, S. Nishi, N. Todaka, S. Takeshita, J. Taura, H. Takahashi*, Y. Nishimura*, K. Tatani*, M. Kawamura, H. Nakayama, T. Nagano*, K. Ohno*, H. Iwamoto*, S. Kadomura and T. Hirayama, Sony Semiconductor Manufacturing, *Sony Semiconductor Solutions

We have successfully mass-produced novel stacked back-illuminated CMOS image sensors. In the new CIS, we introduced advanced Cu2Cu hybrid bonding that we had developed. The electrical test results showed that our robust Cu2Cu hybrid bonding achieved remarkable connectivity and reliability. The performance of image sensor was also investigated

8.5 An Over 1Mfps Global Shutter CMOS Image Sensor with 480 Frame Storage Using Vertical Analog Memory Integration,
M. Suzuki*, M. Suzuki*, R. Kuroda*, Y. Kumagai, A. Chiba, N. Miura, N. Kuriyama and S. Sugawa*, LAPIS Semiconductor Miyagi Co., Ltd., *Tohoku University

An over 1Mfps global shutter CMOS image sensor with 480 analog memories/pixel is presented using developed vertical analog memory integration technology. The fabricated prototype chip with 96H×128V pixels achieved ultra high speed video capturing at 1Mfps with 480 and 960 frames by full pixel and checkered-pattern half pixel modes, respectively.

8.6 A 1.8e- Temporal Noise Over 90dB Dynamic Range 4k2k Super 35mm Format Seamless Global Shutter CMOS Image Sensor with Multiple Accumulation Shutter Technology,
K. Kawabata, M. Kobayashi, Y. Onuki, H. Sekine, T. Tsuboi, Y. Matsuno, H. Takahashi, S. Inoue and T. Ichikawa, Canon Inc.

A low noise and high dynamic range global shutter (GS) CMOS image sensor (CIS) with multiple accumulation shutter technology is described. The pixel having a 6.4μm pitch, achieved 1.8e- temporal noise and full well capacity of 70,000e- with charge domain memory, corresponding to 92dB dynamic range in 30fps operation. In the signal readout procedure, light exposure and signal readout are executed simultaneously, hence the seamless signal accumulation can be carried out.

8.7 Four-Directional Pixel-Wise Polarization CMOS Image Sensor Using Air-Gap Wire Grid on 2.5-µm Back-Illuminated Pixels,
T. Yamazaki, Y. Maruyama, Y. Uesaka, M. Nakamura, Y. Matoba, T. Terada, K. Komori, Y. Ohba, S. Arakawa, Y. Hirasawa*, Y. Kondo*, J. Murayama*, K. Akiyama, Y. Oike, S. Sato and T. Ezaki, Sony Semiconductor Solutions, *Sony Semiconductor Manufacturing

This paper presents a four-directional pixel-wise polarization CMOS image sensor using an air-gap wire grid on 2.5µm back-illuminated pixels. The 150nm-pitch air-gap wire grid polarizer achieved the smallest polarization pixel with a transmittance of 63.3% and an extinction ratio of 85 at 550nm, realizing various mega-pixel fusion-imaging applications.

14.6 Current Status and Challenges of the Modeling of Organic Photodiodes and Solar Cells (Invited),
R. R. Clerc, B. Bouthinon*, M. Mohankumar**, P. Rannou**, J. Vaillant***, T. Maindron***, B. Racine***, Y.-F. Chen^, L. Hirsch^, J.-M. Verilhac^^, A. Pereira^^ and A. Revaux^^, Institut d Optique Graduate School, CNRS *ISORG, **INAC, CEA, ***CEA LETI, ^University of Bordeaux, ^^CEA, LITEN

Progress in the modeling of charge transport in solution processed solar cells and photodiodes is reviewed. Through several examples involving modeling and original experiments, the role of intentional doping, structural defects and oxygen contamination is discussed.

32.4 High-detectivity Printed Organic Photodiodes for Large Area Flexible Imagers (Invited),
A. Pierre and A. Arias, University of California, Berkeley

32.5 Dual-Gate Photosensitive FIN-TFT with High Photoconductive Gain and Near-UV to NearIR Responsivity,
H. Ou, K. Wang, J. Chen, A. Nathan*, S. Z. Deng and N. Xu, Sun Yat-sen Univeristy, *University of Cambridge

We report the first three-dimensional dual-gate photosensitive a-Si:H thin-film transistor operating in the sub-threshold regime for low-level light detection. The measured photoconductive gain is greater than 100 with photo-response ranging from near- ultraviolet to near-infrared wavelengths, making it a potential candidate as an image sensor for UV, visible, IR and X-rays.

32.6 Extending the Functionality of FDSOI N- and P-FETs to Light Sensing,
L. Kadura, L. Grenouillet, T. Bedecarrats, O. Rozeau, N. Rambal, P. Scheiblin, C. Tabone, D. Blachier, O. Faynot, A. Chelnokov and M. Vinet, CEA LETI

We demonstrate that FDSOI transistors co- integrated with a diode implemented below the buried oxide (BOX) become strongly sensitive to visible light. The carriers photogenerated in the diode create a Light Induced VT Shift (LIVS) in both NFET & PFET transistors by means of capacitive coupling, without direct electrical connection between the photodiode and the sensing transistor. This optical back biasing effect is carefully examined as a function of both transistor and diode technological parameters. The experimental results are supported by TCAD simulations, suggesting that the proposed FDSOI/photodiode co-integration scheme can be used for efficient photodetectors. We also study the transient effects, and propose an efficient reset mechanism. Finally, we demonstrate for the first time that SRAM cells can be made controllable by light illumination.

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