"We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence of these traps causes degradation of the transistors electrical performance, altering the oxide electric field and shifting the flat-band voltage, and strongly degrades also reliability. Results from Time-Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements outline the impact of those border traps on the lifetime prediction."
"TDDB measurements were performed on n-channel Tx at 125C, applying a gate stress voltage Vstress in the range +7 to +7.6V. For each Vstress several samples were tested and the time-to-breakdown was measured adopting the three criteria defined in the JEDEC standard JESD92 [21]. For each stress condition, the fit of the Weibull distribution of the time-to-breakdown values gave the corresponding Time-to Failure (TTF). Then, the TTFs were plotted vs. Vstress in a log-log scale and the lifetime at the operating gate voltage was extrapolated with a power law (E-model [22]).
NBTI measurements were performed on p-channel Tx at 125C, applying Vstress in the range -3 to -4V. Again, several Tx were tested. Following the JEDEC standard JESD90 [23], in this case, lifetime is defined as the stress time required to have a 10% shift of the nominal VT. The VT shift has a power law dependence on the stress time and the lifetime value at the operating gate voltage could be extrapolated."
"Noise and charge pumping measurements denoted the presence of donor-like border traps in the gate oxide, which were absent in the Front-Side Illuminated configuration. The trap density follows an exponential dependence on the distance from the interface and reaches the value 2x10e17 cm-3 at 1.8 nm. Electrical measurements performed at different steps during the manufacturing process demonstrated that those border traps are created during the process loop of the Back-Side configuration, consisting of wafer upside flipping, bonding, thinning and VIA opening.
Traps warp the oxide electric field and shift the flat-band voltage with respect to the Front-Side configuration, as if a positive charge centroid of 1.6x10e-8 C/cm2 at 1.7 nm was present in Back-Side configuration, altering the drain and gate current curves.
We found that the donor-like border traps affect also the Back-Side device long term performance. Time Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements were performed to evaluate lifetime. As expected, the role of border traps in the lifetime prediction is different in the two cases, but the reliability degradation of Back-Side with respect to Front-Side-Illuminated CMOS Image Sensors is evident in any case."
Update: Here is comment from Felice Russo:
The following comments intend to clarify the scope of the paper “Performance and reliability degradation of CMOS Image Sensors in Back-Side Illuminated configuration”.
The title reported in the Image Sensor Blog, “LFoundry Data shows that BSI Sensors are Less Reliable than FSI”, leads to a conclusion different from the intent of the authors. The purpose of the paper was to evaluate potential reliability failure mechanisms, intrinsic to a particular BSI process flow, rather than highlighting a general BSI reliability weakness. BSI sensors produced at LFoundry incorporate numerous process techniques to exceed all product reliability requirements.
It is widely accepted [Ref.1-3] that the BSI process is sensitive to charging effects, independent of the specific process flow and production line. It may cause an oxide degradation, mainly related to the presence of additional distributions of donor-like traps in the oxide, located within a tunneling distance from the silicon-oxide interface (border/slow traps) and likely linked to an oxygen vacancy.
The work, published by the University, was based on wafer level characterization data, collected in 2018 using dedicated test structures fabricated with process conditions properly modified to emphasize the influence of the main BSI process steps on the trap generation.
To address these potential intrinsic failure mechanisms, several engineering solutions have been implemented to meet all reliability requirements up to automotive grade. Our earlier published work, [Ref.4], shows BSI can match FSI TDDB lifetime with the properly engineered solutions. Understandably not all solutions can be published.
Results have been used to further improve the performance of BSI products and to identify subsequent innovative solutions for the future generations of BSI sensors.
References:
[1] J. P. Gambino et al., “Device reliability for CMOS image sensors with backside through-silicon vias”, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), 2018
[2] Lahav et al., “BSI complementary metal-oxide-semiconductor (CMOS) imager sensors”, in High performance Silicon Imaging, Second Edition, Edited by D. Durini, 2014
[3] S. G. Wuu et al., “A manufacturing BSI illumination technology using bulk-Si substrate for Advanced CMOS Image sensors”, in Proceedings of the International Image Sensor Workshop, 2009
[4] A Vici et al., “Through-silicon-trench in back-side-illuminated cmos image sensors for the improvement of gate oxide long term performance,” in Proceedings of the International Electron Devices Meeting, 2018.
The following comments intend to clarify the scope of the paper “Performance and reliability degradation of CMOS Image Sensors in Back-Side Illuminated configuration”.
ReplyDeleteThe title reported in the Image Sensor Blog, “LFoundry Data shows that BSI Sensors are Less Reliable than FSI”, leads to a conclusion different from the intent of the authors. The purpose of the paper was to evaluate potential reliability failure mechanisms, intrinsic to a particular BSI process flow, rather than highlighting a general BSI reliability weakness. BSI sensors produced at LFoundry incorporate numerous process techniques to exceed all product reliability requirements.
It is widely accepted [Ref.1-3] that the BSI process is sensitive to charging effects, independent of the specific process flow and production line. It may cause an oxide degradation, mainly related to the presence of additional distributions of donor-like traps in the oxide, located within a tunneling distance from the silicon-oxide interface (border/slow traps) and likely linked to an oxygen vacancy.
The work, published by the University, was based on wafer level characterization data, collected in 2018 using dedicated test structures fabricated with process conditions properly modified to emphasize the influence of the main BSI process steps on the trap generation.
To address these potential intrinsic failure mechanisms, several engineering solutions have been implemented to meet all reliability requirements up to automotive grade. Our earlier published work, [Ref.4], shows BSI can match FSI TDDB lifetime with the properly engineered solutions. Understandably not all solutions can be published.
Results have been used to further improve the performance of BSI products and to identify subsequent innovative solutions for the future generations of BSI sensors.
References:
[1] J. P. Gambino et al., “Device reliability for CMOS image sensors with backside through-silicon vias”, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), 2018
[2] Lahav et al., “BSI complementary metal-oxide-semiconductor (CMOS) imager sensors”, in High performance Silicon Imaging, Second Edition, Edited by D. Durini, 2014
[3] S. G. Wuu et al., “A manufacturing BSI illumination technology using bulk-Si substrate for Advanced CMOS Image sensors”, in Proceedings of the International Image Sensor Workshop, 2009
[4] A Vici et al., “Through-silicon-trench in back-side-illuminated cmos image sensors for the improvement of gate oxide long term performance,” in Proceedings of the International Electron Devices Meeting, 2018.