The Vision P5 core includes an expanded and optimized Instruction Set Architecture (ISA) targeting mobile, ADAS (which includes pedestrian detection, traffic sign recognition, lane tracking, adaptive cruise control, and accident avoidance) and IoT systems.
The Vision P5 core includes these new features:
- Wide 1024-bit memory interface with SuperGather technology for maximum performance on the complex data patterns of vision processing
- Up to 4 vector ALU operations per cycle, each with up to 64-way data parallelism
- Up to 5 instructions issued per cycle from 128-bit wide instruction delivering increased operation parallelism
- Enhanced 8-,16- and 32-bit ISA tuned for vision/imaging applications
- Optional 16-way IEEE single-precision vector floating-point processing unit delivering a massive 32GFLOPs at 1GHz
EETimes believes that such kind of a processor could increase the number of cameras in smartphone from 2 to 4.