Monday, January 23, 2012

Sony Announces Stacked BSI Sensor

Sony announces that it has developed a new next-generation BSI sensor placing the BSI pixel array layer onto a signal processing chip serving as a supporting substrate for the thin BSI array layer:

The advantages of stacked structure are:

  • Adopting pixel array processes specialized for superior image quality
  • Faster speeds and lower power consumption by adopting the leading process for the processing circuit section

As the first step towards the commercialization of its new CMOS image sensors, Sony has developed a model with built-in signal processing functionality. Samples will be shipped from March, 2012. Accordingly, models have been developed with Sony’s unique "RGBW Coding" function, which facilitates low noise, high quality image capture even in low light condition, and the proprietary "HDR Movie" function improving color when taking pictures against bright light.

Update: JCN Network adds few more words on the "RGBW Coding" and "HDR Movie" features and product launch schedules.

"...while the individual pixels of the newly developed models are extremely minute at 1.12um, the incorporation of the "RBGW Coding" function has realized a SN ratio (signal-to-noise ratio) equivalent to that of a unit pixel size of 1.4um under conventional methods, which in turn has enables the image sensors to achieve a higher resolution at a more compact size.

The new models are also able to output signals through the conventional RGB method, thus there is no need to change the signal processing adopted in existing devices.

"HDR Movie" uses "two different exposure conditions within a single screen shooting and conducts the appropriate signal processing for the captured image information under each optimal exposure condition. This process generates an image with a broad dynamic range and enables shooting of both the background and subject matter with brilliant colors even in a bright environment."

"Upcoming product launches (plan):
  • Type 1/4 Stacked CMOS Image Sensor with approx. 8.0 effective megapixels (equipped with camera signal processing function) - Sample shipments planned for March, 2012
  • Type 1/3.06 Stacked CMOS Image Sensor with approx. 13.0 effective megapixels (equipped with "RGBW Coding" and "HDR Movie" functions) - Sample shipments planned for June, 2012
  • Type 1/4 Stacked CMOS Image Sensor with approx. 8.0 effective megapixels (equipped with "RGBW Coding" and "HDR Movie" functions) - Sample shipments planned for August, 2012"

Update #2: Another Sony PR shows "RGBW Coding" advantage at low light and "HDR Movie" video (Youtube version):

Comparison of Sample pictures in low-light setting (10 lux)


  1. Is this based on a single substrat or based on coupled dual substrat ?

    Thanks !

    -yang ni

  2. The Sony announcement says the pixels and circuitry are made on individual chips, and then joined together.

  3. How they connect the circuit section and pixel section? I suppose they use TSV. Is this done at wafer level(then how they manage the yield) or done at chip level(then how's the cost)? What's the reliability performance?

  4. @ "How they connect the circuit section and pixel section?"

    From W. Shakespeare's early image sensor paper Hamlet:

    "Ay, there's the rub,
    For in that sleep of death, what dreams may come,
    When we have shuffled off this mortal coil,
    Must give us pause."

    The anthropomorphic signal treatment probably doesn't fly with today's journal editors, but I'd say there definitely are some throughput challenges when it comes to getting the signals from one chip to the other.

    Hamlet goes on to state:

    "Thus Conscience does make Cowards of us all,
    And thus the Native hue of Resolution
    Is sicklied o'er, with the pale cast of Thought,
    And enterprises of great pitch and moment,
    With this regard their Currents turn awry,
    And lose the name of Action."


  5. This is why they licensed Ziptronix technology not long ago.

  6. OV has RGBW and stacked BSI sensor patents that they have purchased from Kodak. I wonder if they are working on the same type of sensor...

  7. It seems Sony is just way ahead of the rest...Hopefully others can leverage ziptronix technology too...

  8. In the stacked structure is the signal transfer happening after ADC? Digital domain would perhaps seem slightly easier than doing it from column itself in analog domain (while even just digital domain signal transfer would is still a great achievement :) )..Any thoughts??

  9. Whether ADC outputs or ADC inputs are being passed between chips, there's no free lunch. The data rates are just too high either way. My guess would be that the ADC section is still on the imager chip, with a lot of the chip area saved by moving the remaining ISP circuitry to the other chip occupied by digital bus pads. It would be fascinating to see the design details, but the marketing material won't ever include them, just the colorful-polygon abstraction shown here. Maybe in 18 months we'll see some patents with almost-equally-abstract descriptions but enough information to tease out specifics.

  10. or in 18 months we will see chipworks analysis of the silicon processing steps. Is there enough ISP logic if it were a non RGBW processing logic to save area and move it to the carrier wafer? Seems only optimized for ISP which can process RGBW and HDR. Also, is it possible to have 45nm for the logic chip and higher node for image sensor chip?


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