Tech-On published an article and few slides from the Sony 8MP, 1.12um-pixel stacked sensor presentation at ISSCC 2013. The 90nm-processed pixel layer has only high voltage transistors and also contains row drivers and the comparator part of the column-parallel ADCs, with TSV interconnects on the periphery. The bottom logic area is processed in 65nm with LV and HV transistors, and integrates the counter portion of the column ADCs, row decoders, ISP, timing controls, etc.
Sony does not tell the exact details of its TSV processing, but shows the stacked chips cross-section:
The sensor spec slide mentions 5Ke full well - very impressive for a 1.12um pixel:
Tech-On article shows many more slides from the presentation.