Tuesday, February 26, 2013

Sony and Stanford University Develop Compressive Sensing Imager

IEEE Spectrum: Oike from Sony and Stanford University Prof. El Gamal design a compressive image sensor. 256- by 256-pixel image sensor contains associated electronics that can sum random combinations of analog pixel values as it’s making its A-to-D conversions. The digital output of this chip is thus already in compressed form. Depending on how it’s configured, the chip can slash energy consumption by as much as a factor of 15.

The chip is not the first to perform random-pixel summing electronically, but it is the first to capture many different random combinations simultaneously, doing away with the need to take multiple images for each compressed frame. This is a significant accomplishment, according to other experts. "It’s a clever implementation of the compressed-sensing idea," says Richard Baraniuk, a professor of electrical and computer engineering at Rice University, in Houston, and a cofounder of InView Technology.


  1. I love a good PR when I see one. I am also very keen on seeing how this design is different or an improvement over the EPFL CMOS implementation I featured five years ago (http://nuit-blanche.blogspot.com/2008/10/cs-epfl-cmos-cs-imager-compressive.html) or even the earlier Georgia Tech tranform imager ( http://cadsp.ece.gatech.edu/ti.shtml, also see: http://nuit-blanche.blogspot.com/2008/05/cs-compressed-dna-microarrays-and.html )

  2. From the paper:

    "In [18], [19] (the EPFL implementation), CS is implemented by shifting a random digital pattern representing a measurement matrix via a shift register distributed over the pixel array (see Fig. 1(d)). The currents from the pixels with the pattern in the same column are summed over one line while the currents from the pixels with the pattern are summed over a second column line. The total weighted sum is then performed again in analog at the chip level. This implementation requires multiple shot image capture, is not scalable due to the large pixel size, and suffers from low SNR due to pixel design and analog summation."

  3. As mentioned in the above comments, single-shot imaging makes it really practical. And the implementation looks smarter than other approaches. Adopting incremental sigma delta ADC is really nice. But I want to see more sample pictures other than the fingerprint in the ISSCC paper.

    1. You can see some other pictures in J. Solid-State Circuits 48(1):318-328 (2013).


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