Wednesday, November 24, 2010

CMOSIS Develops Dual Gain Readout HDR Sensor

New Electronics: CMOSIS has demonstrated a 1MP image sensor featuring dual gain readout to reach DR of more than 89.5dB. The DR is increased by two approaches. First, the dark noise is said to be reduced. Second, the integration of the image charge is said to take place simultaneously at low and high amplification settings. This dual gain readout results in two different images which are read out sequentially and combined externally into one final image. The sensor has twice the number of column amplifiers than columns and the gain of each amplifier is programmable up to 16.

This approach is to be used in a number of future products with different pixel size, frame rate, etc.

Update: Electronics Weekly too published an article about the new CMOSIS 1MP imager dubbed CLN1000 and featuring 10um pixels. The sensor consumes 300 to 350mW, and is housed in a JLCC-84 package. The article also states low dark noise of less than 3.4e- at a full well capacity of 100 ke-. EETimes quotes the same numbers too.

Update #2: Photonics Online published an article about the CMOSIS prototype too.

Update #3: Here is the original CMOSIS PR.


  1. Anywhere I can find the real image or video performance?

  2. what is new? dual gain pixels and dual gain read-out have been presented before. aren't they getting into patent issues?

  3. Indeed, Michelle Wang did this as part of her Ph.D. thesis and it was presented at Lake Tahoe in 2001. A copy of her paper is here:
    I think the patent is owned by Micron these days since it was a Photobit paper. I doubt Micron would prosecute this unless there was a lot of money at stake. There isn't at this time.
    Two gains were used in some CCDs even prior to that.

    An "easy" way to confirm HDR operation by counting interference rings was also presented in that paper. I think every HDR paper should use such an image to prove HDR operation.

  4. Lawyers like to make broad claims, but dual gain in general will not stand up. A special implementation of dual gain could be upheld if it is novel. A pixel with dual gain is not novel.

  5. Anon - always better to back up your broad assertions with real information. What is the prior art that you refer to?

    Meanwhile, after further thought, our patent was clear about doing the two gains at different times (i.e. sequentially by changing a switch in the amplifier), probably due to prior art issues - I don't recall at this time. But, you can find a number of cited prior art patents in 6,734,905.

    The CMOSIS chip apparently does the two gains simultaneously, so as far as '905 goes, there would be no infringement anyway.

    I am glad to see some of these HDR concepts put into practice. It is about time.

  6. This is NOT by using two gains in the readout path (like Michelle Wang did in 2001). We'll be submitting a scientific article soon about the trick that we actually use.

    Guy Meynants
    VP R&D, CMOSIS nv.

  7. I don't understand why a trick is needed. 100,000/3.4 = 89.4 db. Is it just to avoid the need for 16-bit ADCs? Digitizing in two ranges, though, means that the smallest changes cannot be represented at the highest signal levels. Could this device be used with 16-bit (or deeper) ADCs?

  8. The photon shot noise at 100Ke signal level is about 300e. If one uses 16b ADC, its LSBs would be wasted at large signal levels. They only needed at small signal. So such a dynamic scaling of resolution makes sense.

  9. I'll be interested to see how this is different than Fairchild's SCMOS dual-gain low-noise approach.

  10. but a simple Gamma correction is enough and also some non-linear coding schemas like u-Law or A-law in speech coding. What's new really?

  11. Gamma correction is enough, if applied in the analog domain before the ADC. Then an 8-bit ADC can deliver similar results to a 16-bit one. However, in most designs Gamma is applied digitally after demosaicing. Thus ADC might or might not need some tricks to scale its resolution across the DR, depending on the ADC design and the DR to cover.


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