Paper on 3D-stacked InGaAs/InP SPAD

In a "hot-off-the-press" paper in Optics Express titled "Room-temperature, 96×96 pixel 3D-stacked InGaAs/InP SPAD sensor with complementary gating for flash LiDAR", Yildirim et al. from EPFL/Fraunhofer/FBH write:

A room-temperature 3D-stacked flash LiDAR sensor is presented for the short-wave infrared (SWIR). The 96×96 InGaAs-InP SPAD array in the top tier is biased by a circuit at the bottom tier that implements a complementary cascoded gating at the pixel level to control noise and afterpulsing. The bottom-tier chip is fabricated in a 110-nm CMOS technology. The sensor is tested with a 1550nm laser operating at 100μW to 3.1mW average power. The SPADs are gated with 3ns pulses with 500ps skew. Intensity images and depth maps are shown both indoors and outdoors at 10m in 120 klux background light with telemetry up to 100m, having better than 2% accuracy.

Open access link: https://doi.org/10.1364/OE.585267

Proposed complementary optical gating pixel for InGaAs SPADs (a) arranged in a 9696 array (b) and its timing diagram (c).

Micrograph of the bottom tier (a) and 3D-stacked chip micrograph (b). Illustration of the indium bump bonding scheme (c).
 

Outdoors flash LiDAR images with 120klux background sunlight. The scene, intensity image and depth image shown for 3m(a-c) and 10m(d-f).