IEDM Image Sensors Session Dec 10 (today!)

Program link: https://iedm25.mapyourshow.com/8_0/sessions/session-details.cfm?ScheduleID=36&

Advanced Image Sensors
Wednesday, December 10
1:30 PM - 5:20 PM PST

This session includes 8 papers on the latest in image sensor technology. The first is an invited paper on progress in flash LiDAR using heterodyne detection. The next two papers present HDR imagers using LOFIC pixels that reach or exceed 120dB. This is followed by papers on specialty imagers, the first one describing an all-organic flexible imager, followed by an extremely high frame-rate burst CIS sensor. The final three papers of the session cover the latest technologies for shrinking pixels to sub-micron dimensions. Of special note is the last paper, which shrinks the dual-photodiode pixel to 0.7um.

3D FMCW Wide-angle Flash Lidar: Towards System Integration and In-pixel Frequency Measurement (Invited)

The Frequency Modulated Continuous Wave Light detection and ranging (FMCW Lidar) usually scans the scene point by point, and measures the distance by a Fourier Transform (FT) of the heterodyne signal. A promising solution for higher frame rate with larger image resolution is the flash version of the FMCW Lidar, using floodlight illumination and an image sensor. We first review our recent achievements of FMCW flash Lidar system developments with commercially available components and post-processing. Because FT is difficult to implement in small pixels, we then introduce the principle of a heterodyne image sensor with in-pixel frequency measurement combined with a multi-chirp laser modulation strategy, targeting video rate real-time measurements. 

A 120 dB Dynamic Range 3D Stacked 2-Stage LOFIC CMOS Image Sensor with Illuminance-Adaptive Signal Selection Function

This work presents a 3D stacked 2-stage lateral overflow integration capacitor (LOFIC) CMOS image sensor with illumination adaptive signal selection function. To reduce the high data rates of conventional wide dynamic range sensors, this work proposes an illuminance-adaptive signal selection circuit that non-destructively determines the light intensity level using electrons accumulated in the first stage of LOFIC. This allows the developed sensor to selectively output one or two most appropriate signals out of three, reducing the data rate while maintaining a wide dynamic range. Furthermore, a 3D-stacked Si trench capacitor is employed to achieve over 8.6Me- FWC with 5.6 µm pixel pitch. The fabricated chip demonstrates a dynamic range of 120 dB with selected signal readout and a maximum SNR of 67.5 dB. 

A 129 dB Dynamic Range Triple Readout CMOS Image Sensor with FWC Enhancement Technology

We present a 2.1 μm pixel CMOS image sensor for automotive applications achieving 129 dB single exposure dynamic range with triple readout. The advanced sub-pixel architecture incorporates FDTI, conformal doping and 3D-MIM technologies, significantly enhancing full-well capacity. The sensor enables a seamless triple-image composition with 29 dB SNR at connection points, suitable for high-temperature automotive environments. 

Flexible 256×256 All-Organic-Transistor Active-Matrix Optical Imager with Integrated Gate Driver

Solution-processed organic thin film transistors (OTFTs) provide a promising platform for truly flexible, large-area integrated sensor systems. Here, an all-organic-transistor active-matrix imager using OTFTs for both the backplane and optical sensing layer is developed. Through reducing the density of states at the channel interface for a steep subthreshold swing and low dark current, the resulting organic phototransistor (OPT) presents a high detectivity of 2.2×1016 Jones. The OPT is stacked on top of an OTFT switch with a high ON/OFF ratio of 4.7×1010 to form the active matrix and the gate driver is also integrated. Finally, a 256 × 256 (213 PPI) flexible active-matrix imager is demonstrated for fingerprint and low-distortion imaging with the constructed real-time imaging system. 

A Global Shutter Burst CMOS Image Sensor with 6-Tpixel/s Readout Speed, 256-recording Frames and -170dB Parasitic Light Sensitivity

This paper presents an ultra-high-speed (UHS) global shutter burst CMOS image sensor (CIS) featuring pixelwis analog memory arrays. The developed CIS with 628H x 480V pixels achieves a maximum frame rate of 20 Mfps and a readout speed of 6.03 Tpixel/s. A recording length of 256 frames and a parasitic light sensitivity (PLS) of -170 dB were also achieved simultaneously in a UHS camera. This low PLS is achieved through comprehensive metal shielding of the pixel circuit and memory regions, and by the spatial separation between the photodiode and memory regions, implemented using Si trench capacitors. The introduced bias adjustment circuit compensates for voltage variations among pixel positions due to the ground resistance and pixel circuit current during the pixel driving period, enabling high-resolution video recording with an effective 628H x 480V pixels and a 48 μm pitch. 

Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS

This study presents a 2-Layer transistor pixel stacked 0.8-µm dual-pixel (DP) CIS with silicon-on-insulator (SOI) fin field-effect transistor (FinFET) technology. The application of SOI FinFETs as pixel transistors, featuring a body-less configuration on buried oxide, reduces parasitic capacitance at the floating diffusion node, thereby enhancing conversion gain and noise characteristics. The SOI FinFET achieves improved transconductance and source follower gain compared to a previous pixel FinFET. The resolution of challenges associated with the SOI structure is demonstrated through a 0.8μm DP CIS with SOI FinFETs. 

A 0.43µm Quad-Photodiode CMOS Image Sensor by 3-Wafer-Stacking and Dual-Backside Deep Trench Isolation Technologies

Scaling pixel pitch below 0.5um has become highly challenging in conventional 2-wafer stacked CMOS image sensors due to the limited silicon area shared among photodiodes, photodiode-photodiode isolation, and the associated functional transistors, while maintaining the excellent pixel performance. In this work, several advanced pixel technologies, including 3-wafer stacking, dual-backside deep trench isolation, and enhanced composite metal grid, were proposed and employed, to realize the world's smallest 0.43 µm pitch quad-photodiode pixel, achieving exceptional performance metrics of full well capacity of 6000 e-, dark current of 1.3 e-/s, and read noise of 1.5 e-rms, without degradation in conversion gain. 

A 2-layer, 0.7μm-pitch Dual Photodiode Pixel CMOS Image Sensors with Metaphotonic Color Router

In this article, a world’s smallest 0.7μm-pitch dual photodiode pixel is presented. We integrated 2-layer pixel with hybrid Cu-Cu bonding process only, without introducing pixel-level deep contacts. By optimizing layout of Cu pad layer, we suppressed capacitive coupling between neighboring floating diffusion nodes, still achieved similar conversion gain compared to that of 0.7μm-pitch, 1-layer single photodiode pixel. We overcome the degradation of the auto-focus (AF) separation ratio by incorporating multi-focal, metaphotonic color routers (MPCR).