Thursday, June 18, 2026

400x400 pixel stacked CIS HDR sensor for AR/VR applications

In a June 2026 paper titled "A 400×400 3.24-μm 117-dB Dynamic Range Three-Layer Stacked Digital Pixel Sensor With Triple Quantization and Fixed Pattern Noise Correction" published in IEEE Trans. Electron Devices, a team from Brillnics, Meta, and SesameAI* write:

This article presents a 400×400 digital pixel sensor (DPS) with a 3.24 μm pixel pitch, fabricated using a 45/40/40 nm three-layer stacked process. The sensor achieves single-exposure high dynamic range (SEHDR) through overlapped triple quantization (3Q), fixed pattern noise correction (FPN-C), and black level correction (BLC). An on-chip image signal processor (ISP) is integrated to support defect pixel correction (DPC), SEHDR linearization, and gamma correction. Sparse transmission (ST) is incorporated to reduce transmitted data volume and, consequently, transmission power consumption. A wafer-level chip-scale package (WLCSP) with two redistribution layers (RDLs) is employed, resulting in a compact form factor of 2.47×1.85 mm^2. This work achieves a dynamic range (DR) of 117 dB while consuming 2.45 mW at 30 frames/s (fps), yielding a figure of merit (FoM) of 0.0046 e- rms  pJ, and is developed to meet the growing demands of augmented reality (AR) and virtual reality (VR) applications.

Full paper: https://doi.org/10.1109/TED.2026.3687537 

 











 

* Sesame AI (https://www.sesame.com/) is developing "conversational AI agents", with a smart glasses product slated for 2027.

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