Friday, February 16, 2007

Micron 1.75um Pixel Paper on ISSCC'07

EETimes gives a few bits from Micron's ISSCC presentation a few days ago. The paper was presented by KB Cho, a senior VLSI design engineer from Micron's Imaging Design Center in Pasadena. The 8MP MT9E001 imager includes a low-noise signal readout chain, a 12-bit analog-to-digital converter, an internal phase-locked loop and a 12- bit parallel interface to output pixel data at up to 96 megapixels per second (Mp/s), according to the paper.

It uses top and bottom multiple channels with a double-data-rate analog signal readout at a rate of 96 Mp/s, which results in 15 frames per second (fps) at full resolution and 30 fps at VGA resolution. Operating power consumption of the chip in full resolution at 11 fps is less than 400mW. With dynamic power management, a reduction of more than 30 percent of total power is achieved by turning off analog blocks for a period of time.

The imager is fabricated in a standard 0.13-micron CMOS process. Cho said following the presentation that the design includes "more than two" metal layers, but declined to specify further.

"In my opinion, we outperform conventional CCD sensors with the same optical format," Cho said, citing low power consumption, high speed, higher signal-to-noise ratio and low-light sensitivity. "One of the strengths of this chip is that we have a high conversion gain. That gives us quite a high sensitivity."

A Micron spokeswoman said the MT9E001 is currently sampling and is expected to be in volume production late this quarter or early in the second quarter.

In 2006, roughly 79 percent of digital still cameras employed CCD image sensors, according to IC Insights. By 2009, the firm expects CMOS image sensors to surpass CCD image sensors in digital still camera market share.

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