Thursday, July 24, 2008

Yole Predicts 3D-TSV Revolution

Research and Markets published interesting predictions about 3D-TSV packaging future, probably originated from Yole Developpement:

"WL-CSP CMOS image sensors are on the point to leave their traditional edge interconnects configuration for going to "real" 3D-TSV architectures as soon as this year. Vias will be partially or completely filled, depending on via filling approach being developed (Copper for partial filling, Poly-Silicon or Tungsten for completely filled vias). Additionally, we clearly see the number of I/Os expanding to several hundreds of interconnects per chip with a trend to stack the DSP chips under the image sensor chip itself."

No comments:

Post a Comment

All comments are moderated to avoid spam and personal attacks.