Wednesday, April 25, 2012

Column Settling Speedup Proposal

Patent application US20120091323 by Shoji Kawahito proposes to speed-up the column voltage sampling onto a big capacitor. The idea is to add small capacitor sampler 17 that samples the column first, then accelerates charging of the main sampling cap C1i. It's quite self-explanatory based on the schematics and the timing diagram below (Block 11 is a pixel driving column Vcol):

There are few other similar ideas, like pre-charging the large C1i capacitor through a unity-gain buffer and then completing the final charge stage directly from column. One can add a little bit high pass filtering in the buffer to compensate for low-pass nature of the pixel+column cap path.

On the other hand, in Kawahito's idea one can add a small time delay or a phase shift in the trans-impedance amplifier 25 on the figure above to achieve a kind of inductive impedance in the column load and get some speed up from it.


  1. Please correct me if I am wrong: you first need to charge Cp1 and C17 with the source follower of the pixel. Cp1 is often larger than Cs especially in large arrays..

  2. You probably meant C2i, not C17, right?

    The patent application assumes that Cp1 < C2i < C1i, as stated in Claim #2 and in "Solution to Problem" section, paragraph 2. You are right, it might be less effective when Cp1 is a dominating cap.

  3. Here are some other patent application publications directed to speeding up the settling time of a column or preventing eclipsing.

    US 20060256220
    US 20060227226
    US 20060044414
    US 20110019053
    US 20080284891
    US 20060203123
    US 20040079973
    US 20060278809
    US 20060238634
    US 20100118174
    US 20070091193

  4. very useful indeed!

  5. what is the main advantage here compared to use simply the amp as a follower?

  6. By adding buffer 17 you increase the bandwidth of the noise and also add extra noise. Probably noise is not crucial in the application where you use this structure but wouldn't it be easier to just lower the sampling capacitance c1i?

  7. I've made a SPICE simulation on this circuit. There are 2 problems:
    1. the amplifier introduces an offset voltage
    2. it takes the same RC decay for the column driver to absorbe this offset on the big cap.

    So all in all, the utility of this circuit is limited to my opinion. Any comments please?

    1. The amplifier offset should be cancelled by auto-zero. Still, the big cap needs some time to settle on noise, you are right. As the last graph in the post shows, the gain might be between 1.5 to 2.5, depending on the settling accuracy.

    2. Vladimir, the offset cannot be remmoved by auto-zero. Because the auto-zero is not set at the input voltage, so the difference between the reset level and the signal level has to be corrected by the amplifier and this causes offset.

    3. I do not agree. Basically, one can zero the buffer offset when it's connected to a reference voltage, then it remains zero when connected to whatever other signal.


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