Tuesday, April 24, 2012

Image Sensors at 2012 VLSI Circuit Symposium

2012 VLSI Circuit Symposium agenda has been published some time ago. There is no classical image sensor papers this year. Few interesting image sensor related papers are below:

Looks like gesture recognition application blends the border between ToF imagers, THz imaging and mm-band radars (session 7):

A 94GHz mm-Wave to Baseband Pulsed-Radar for Imaging and Gesture Recognition
A. Arbabian, S. Kang*, S. Callender*, J.-C. Chien*, B. Afshar*, A. Niknejad*, Stanford University, *University of California, Berkeley

An integrated phase-coherent and pixel-scalable pulsed-radar transceiver with on-chip tapered loop antennas generates programmable pulses down to 36ps using an integrated 94GHz carrier, frequency synthesized and locked to an external reference. A DLL controls the TX pulse position with 2.28ps resolution, which allows the chip to function as a unit element in a timed-array. The receiver also features a >1.5THz GBW DA as the front-end amplifier, wideband quadrature mixers, and a 26GHz quadrature baseband. Phase coherency allows for ~375μm single-target position resolution by interferometry.

Another imager-like radar works at slightly lower frequency band, but still is a single-chip design:

A UWB IR Timed-Array Radar Using Time-Shifted Direct-Sampling Architecture
C.-M. Lai, K.-W. Tan, L.-Y. Yu, Y.-J. Chen, J.-W. Huang, S.-C. Lai, F.-H. Chung, C.-F. Yen, J.-M. Wu, P.-C. Huang, K.-J. Chang, S.-Y. Huang, T.-S. Chu, National Tsing Hua University

A UWB impulse radio (IR) timed-array radar using time-shifted direct-sampling architecture is presented. The transmitter array can generate and send a variety of 10GS/s pulses towards targets. The receiver array samples the reflected signal in RF domain directly by time interleaved sampling with equivalent sampling rate of 20 GS/s. The radar system can determine time of arrival (TOA) and direction of arrival (DOA) through time-shifted sampling edges which are generated by on-chip digital-to-time converters (DTC). The proposed architecture has range and azimuth resolution of 0.75 cm and 3 degree respectively. This prototype is implemented in a 0.18μm CMOS technology.

While we are dreaming to reach full well of a mega-electron, it looks like HgCdTe guys enjoy measuring their full wells in giga-electrons (Session 15):

An 88dB SNR, 30µm Pixel Pitch Infra-Red Image Sensor with a 2-Step 16 bit A/D Conversion
A. Peizerat, J.-P. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian, CEA-LETI, Minatec

A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320x256 array with 30µm pixel pitch, has been designed in a standard 0.18µm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.


  1. Unrelated to this topic but interesting.


  2. Vladimir,

    The well capacity comparison is really apples and oranges. If you put large silicon photodiodes on an ROIC, then those can have gigaelectron capacity, too. It is the monolithic contruction of most silicon imagers (not possible with HgCdTe) that constrains the well capacity.

    On another subject, 94GHz was proposed at least 20 years ago for passive imaging on the ground at airports because water is transparent at that frequency. The British made some vary nice pictures of planes on the tarmac easily seen at 94 GHZ but completely obscured by fog in the visible. Maybe one of the new THz imagers will be sensitive enough to allow economical resurrection of these programs.


  3. Dave,

    In order to achieve the same 3Ge- full well, one needs 160pF storage capacitance, assuming 3V voltage swing. Even with smart tricks like differential charging (one pin of the cap goes up from 0 to 3V, the other goes down from 3V to 0), one still needs 80pF of storage. I doubt that you can achieve this with a 30x30 um silicon photodiode. You probably mean 10-layer SiLMs or something like that, right?

    1. Vladimir,

      All I am saying is that if someone builds an appropriate array of silicon photodiodes and puts them on an ROIC like those used for infrared imaging, then the ROIC determines the charge storage limit, not the photodiode array. HgCdTe works in a direct injection mode so none of the charge gets stored in the detector elements. The same thing can be done with silicon.

      Regards, Dave

    2. I do not see how you get 80-160pF x 3V in 30um square on ROIC. Indeed, the biggest cap density I've heard of is 8fF/sq. um - at least an order of magnitude lower than one needs.

      Assuming that one uses gate capacitor and that leakage is not important in LWIR, than 17fF/sq. um is what's available with SiO2 dielectric, but then the swing is limited by 1.2V - still an order of magnitude lower.

      If you are lucky and have an access to 28/32nm HKMG process, then your gate cap is 22-25fF/sq.um, but the swing is limited by 1.1V - still far away from the target.

      Something 3D-integrated is needed, like FinFET, SiLM, or the likes.

      Let me know if you have a nicer idea.

  4. No 3D-integration, just use of in pixel charge packets counting. As stated by the authors in a previous paper (SPIE proc. 7834, 2010) "the analog front-end (integrator and comparator) performs a current-to-frequency conversion and the counter evaluates the average frequency by counting the number of signal edges during a given integration time".


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