Thursday, July 21, 2011

Chipworks Discovers Sub-Micron TSVs in Fujifilm-Toshiba BSI Sensors

Chipworks presents more details of its reverse engineering analysis of Toshiba HEW4 BSI sensor found inside Fujufilm F550 EXR camera. The sensor was fabricated using the Toshiba Oita 300 mm wafer line, using a 65 nm logic process adapted to BSI image sensor production.

"The most telling aspect of how the HEW4 BSI chip gets integrated into a chip scale camera module involves the use of very high density arrays of polysilicon filled through silicon vias (TSVs), to form the electrical interconnect between the back side wire bonds and the CMOS integrated circuits on the front of the wafer (Figure 5). These are the first true submicron TSVs that Chipworks has seen deployed in volume production."

Fig. 5. Sub-micron TSVs cross-section

Chipwork says: "the HEW4 device defines a new category of CIS camera module with its closely packed, poly-filled submicron TSVs that connect the back side aluminum bond pads to the front side copper lines. This technology is non-trivial to implement. Once mastered and with appropriate economies of scale in play, however, this advanced TSV process saves valuable silicon area and can reduce the size of the camera module."


  1. Very impressive!

    I measure these as having ~5.6:1 aspect ratio, which is quite high (esp. compared to filled copper TSVs).

  2. Impressive, but I'm missing a ref scale to get information about dimensions and pitch since I do not know how deep is the silicon these TSV get through.

  3. Given that it's BSI, I'd guess that it's around 3┬Ám thick silicon.

  4. Can anyone comment on why and how TSVs are used here? Application of a TSV seems pretty straightforward in imaging systems where there are separate sensing and ROIC chips. However, in a BSI chip, the photo-sensing portion of the back side has to be at the top of any chip stack. Are these TSVs just allowing wire pads to be moved from the front side next to the photo-sensing regions and other circuitry (ADC, etc.) to the back side still next to the photo-sensing regions but over (or under) the other circuitry?

  5. @CDM:

    With BSI, the I/O pads end up on the bottom side of the sensor silicon (which is bonded to a handle wafer so the pads are burried). To get to the pads, you need some means of creating a via through the silicon to the front side metal.

  6. why you need such micro via? You can access to the pads by using normal etching process. The pad size is huge.

    I think that this is for wafer scale packaging and the we need to access to the pad from the bottom of the handling wafer.

  7. I need help understanding this.

    1) Am I right in thinking this is a cross section of a die on an RDL/PCB?
    2) The "sub-micron" vias are the lighter structures under the pad looking things at the top of the stack?
    3) The long structures coming down are via's in the RDL/PCB?

    The only application I can think for this is in 3D integration. I'm still not sure why the bond pads for IC to IC connectivity can be significantly smaller (such that sub-micron vias help increase density) than the pads needed for IC to RDL/PCB connectivity.

    Someone help me out here!

  8. It looks like you are correctly interpreting the picture.

    I think Toshiba has developed these vias for some other project like multi-die 3D integration and just re-used the same technology in its sensors.

  9. Thanks VK. Although, thinking about it again, the scales in the picture don't quite add up. If we are pessimistic and say the TSV is almost 1um then the vias in the RDL must be ~10um. I think in PCB world there is no way to fabricate a 10um via. I believe 75um is pushing the limit at this point. Hmm.


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