Friday, August 07, 2015

ST Combines SF and SEL Transistors

In a push to minimize the number of transistors in pixel while keeping the high readout speed, ST patent application US20150215559 "Pixel circuit with fast read out" by Cedric Tubert proposes to combine SF and SEL transistors in the neighboring rows. What serves as a SF transistor in one row, functions as SEL transistor for another row, and wise versa:


  1. Albert TheuwissenAugust 7, 2015 at 2:48 PM

    This pixel has 8 transistors/cel of 4 pixels, so 2 transistors per pixel. I have seen lower transistor counts by means of the sharing concept. But nevertheless I like this idea very much as well. Nice piece of work. Sometimes life can be simple .... sometimes .....

  2. It's crazy to see how many combinations we can make with so few transistors !
    -yang ni

  3. Yes, clever idea.

    Is there not an extra output bus line going through all the pixels that needs to be toggled between output column bus and VDD on alternate rows? Or am I getting it wrong?

    What is the effect of a 1Kohm switch in series with the VDD?
    Power (cv^2) of charging and discharging each of those column buses?
    Are the odd/even row effects fully correctable through post processing?

    I don't work with small pixels, I have no feel for the pros/cons. The devil is always in the details, and there are now a LOT of details in implementing this clever idea.

  4. Congratulation M. Tubert, it's a clever idea !


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